From: will.deacon@arm•com (Will Deacon)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH] virtio: Try to untangle DMA coherency
Date: Mon, 13 Feb 2017 11:57:59 +0000 [thread overview]
Message-ID: <20170213115758.GK1512@arm.com> (raw)
In-Reply-To: <20170210191409-mutt-send-email-mst@kernel.org>
On Fri, Feb 10, 2017 at 07:16:10PM +0200, Michael S. Tsirkin wrote:
> On Thu, Feb 09, 2017 at 06:31:18PM +0000, Will Deacon wrote:
> > On ARM (and other archs such as
> > Power), having a mismatch between a cacheable and a non-cacheable mapping
> > can result in a loss of coherency between the two (for example, if the
> > non-cacheable gues accesses bypass the cache, but the cacheable host
> > accesses allocate in the cache).
>
> I guess it's an optimization to avoid cache snoops for non-cacheable accesses?
The architecture doesn't rationalise the decision, but a micro-architecture
could indeed implement the optimisation you suggest (and we do observe the
loss of coherency in practice).
Will
next prev parent reply other threads:[~2017-02-13 11:57 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-01 12:25 [PATCH] virtio: Try to untangle DMA coherency Robin Murphy
2017-02-01 14:57 ` Will Deacon
2017-02-01 17:58 ` Rob Herring
2017-02-01 18:09 ` Michael S. Tsirkin
2017-02-01 18:27 ` Will Deacon
2017-02-01 19:19 ` Michael S. Tsirkin
2017-02-02 11:26 ` Will Deacon
2017-02-02 13:34 ` Robin Murphy
2017-02-02 16:16 ` Michael S. Tsirkin
2017-02-02 16:39 ` Marc Zyngier
2017-02-02 16:44 ` Michael S. Tsirkin
2017-02-02 16:30 ` Michael S. Tsirkin
2017-02-02 16:40 ` Will Deacon
2017-02-02 16:45 ` Michael S. Tsirkin
2017-02-09 18:17 ` Michael S. Tsirkin
2017-02-09 18:31 ` Will Deacon
2017-02-09 18:49 ` Michael S. Tsirkin
2017-02-09 18:54 ` Ard Biesheuvel
2017-02-09 18:56 ` Will Deacon
2017-02-10 17:16 ` Michael S. Tsirkin
2017-02-13 11:57 ` Will Deacon [this message]
2017-02-08 12:58 ` Alexander Graf
2017-02-09 20:57 ` Michael S. Tsirkin
2017-02-09 22:20 ` Alexander Graf
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