Subject: [PATCH 1/1] xilinx ps uart: Adding a kernel parameter for the number of xilinx ps uarts

From: [email-masked] (Alan Cox)
Date: Tue, 23 May 2017 21:07:10 +0100

> yep hardcoded max 4 where in probe first free space is found and used
> (range 0-3) but still max3100s statically allocated.
> Shouldn't be this also dynamically allocated?

The code to do the dynamic allocation would be larger than the array of
pointers for the sane worst case.

> I am not quite sure how exactly you want to do this via DT.

Count the number of DT entries for this kind of port and allocate that
many ?

> 
> Also what do you think is a safe maximum number? This is fpga - hundreds
> of pins which can do just uart.
> 
> > There are lots of options better than breaking the "one kernel many
> > platforms" model.  
> 
> Another options is also module parameter and dynamically allocated array
> in cdns_uart_init.

For a given platform the number is constant and they need to be
described, so it seems to make no sense to put it anywhere other than the
DT for that platform.

Why should users have to pass magic config options not use DT as
intended ?

Alan