Subject: Re: [PATCH 1/8] clk: sunxi-ng: h6: Fix clock divider range on some clocks

From: Jernej Škrabec <[email-masked]>
Date: Wed, 02 Dec 2020 17:17:03 +0100

Dne sreda, 02. december 2020 ob 14:54:02 CET je Andre Przywara napisal(a):
> While comparing clocks between the H6 and H616, some of the M factor
> ranges were found to be wrong: the manual says they are only covering
> two bits [1:0], but our code had "5" in the number-of-bits field.
> 
> By writing 0xff into that register in U-Boot and via FEL, it could be
> confirmed that bits [4:2] are indeed masked off, so the manual is right.
> 
> Change to number of bits in the affected clock's description.
> 
> Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
> Signed-off-by: Andre Przywara <[email-masked]>

Reviewed-by: Jernej Skrabec <[email-masked]>

Best regards,
Jernej

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