Subject: LPC3250 periph clock at 13MHz instead of 10.4MHz

From: Alexandre Belloni <[email-masked]>
Date: Tue, 12 Feb 2019 17:52:21 +0100

Hi,

I've been observing a mismatch between the reported periph clock
frequency and the actuall periph clock frequency on a custom board.

clk_summary gives:

 xtal                                 1        1        1    13000000          0     0  50000
    osc                               2        2        1    13000000          0     0  50000
       sys                            1        1        0    13000000          0     0  50000
          hclk_pll                    3        3        0   208000000          0     0  50000
             hclk_div_periph          1        1        0    10400000          0     0  50000
                sysclk_periph_mux       1        1        0    10400000          0     0  50000
                   pclk               4        4        0    10400000          0     0  50000
                      uart5           1        1        0    10400000          0     0  50000
                      timer0          1        1        0    10400000          0     0  50000
                      timer1          1        1        0    10400000          0     0  50000

And this seems quite right when reading the registers using devmem.

But, I observed that the input clock for UART5 seems to be 13MHz. At
9600 bauds, the calculated UnDLM:UnDLL is 68 (which would give
10400000/(16*68) = 9558 bauds) but at the oscilloscope, I see that the
UARt is running close to 12kHz. Forcing the frequency to 13MHz, gives a
divisor of 85 and solves the issue.

Note that this issue will not be seen right away at 115200 bauds because
the divisor is then quite close (6 for 10.4MHz and 7 for 13MHz).

Similarily using an i2c RTC, I can see that the timer is quite off:

# hwclock; sleep 10; hwclock
Tue Feb 12 16:53:09 2019  0.000000 seconds
Tue Feb 12 16:53:17 2019  0.000000 seconds

This is what is expected if the 13MHz input clock is mistaken as 10.4MHz
as 10*10.4/13 = 8s.

This leads me to think that pclk is actually running at 13MHz.

PWR_CTRL is set to 0x16 so the pclk parent should be hclk_div and not
sysclk.

Am I missing something?

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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