Subject: Re: [PATCH 1/2] memory: ti-emif-sram: Add ti_emif_run_hw_leveling for DDR3 hardware leveling

From: Tony Lindgren <[email-masked]>
Date: Tue, 9 Apr 2019 08:33:10 -0700

* [email-masked] <[email-masked]> [190409 15:26]:
> On 4/9/19 8:19 AM, Tony Lindgren wrote:
> > * Tony Lindgren <[email-masked]> [190408 19:34]:
> > > * Dave Gerlach <[email-masked]> [190408 18:31]:
> > > > Tony,
> > > > On 4/2/19 12:24 PM, Tony Lindgren wrote:
> > > > > * Dave Gerlach <[email-masked]> [190402 16:57]:
> > > > > > In certain situations, such as when returning from low power modes, the
> > > > > > EMIF must re-run hardware leveling to properly restore DDR3 access.
> > > > > > 
> > > > > > This is accomplished by introducing a new ti-emif-sram-pm call,
> > > > > > ti_emif_run_hw_leveling, to check if DDR3 is in use and if so, trigger
> > > > > > the full write and read leveling processes.
> > > > > 
> > > > > OK nice that you also consider devices with LPDDR2 then in case we
> > > > > start seeing those.
> > > > 
> > > > Yes, LPDDR2 will work fine with these. Any thoughts on if this series should
> > > > come through you or Santosh?
> > > 
> > > Probably best that I queue these since there's also
> > > arch/arm/mach-omap2 code related changes.
> > 
> > Santosh, is this OK with you? Care to ack the patch?
> > 
> Sure Tony !!
> 
> Acked-by: Santosh Shilimkar <[email-masked]>

Thanks, applying these two patches into omap-for-v5.2/am4-ddr3
branch.

Reagrds,

Tony

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