Subject: Re: LPC3250 periph clock at 13MHz instead of 10.4MHz

From: Alexandre Belloni <[email-masked]>
Date: Wed, 10 Apr 2019 16:18:05 +0200

On 10/04/2019 15:44:43+0200, Alexandre Belloni wrote:
> Hi Vladimir,
> 
> On 13/02/2019 19:21:44+0200, Vladimir Zapolskiy wrote:
> > > Am I missing something?
> > > 
> > 
> > I think I encountered quite a similar issue previously, but under another
> > circumstances, when I begin to modify HCLK PLL clock rate, can you check
> > my comment at https://lore.kernel.org/linux-clk/[email-masked]/
> > and verify if it's about the same problem?
> > 
> > Since the problem hits you also, I plan to spend some time on this weekend
> > to capture more details, fortunately there is a known workaround to pin
> > UART input clock rate to 13MHz, it might be desired to carve it in the code.
> > 
> 
> I'm pretty sure this is the same issue and that it doesn't only affect
> the UARTs but also timers.
> 
> The 2.6.27.8 kernel code would indicated that the timers are only driven
> by sysclk, that is either 13MHz from the oscillator or 13.008896 from
> PLL397. I'm wondering how many other peripherals are affected.
> 

You'll note that this is also true for the watchdog, the driver has:

// NOTE - the driver only uses this value if it can't get the clock rate from the clk_ drivers
#define WDOG_COUNTER_RATE 13000000	/*the counter clock is 13 MHz fixed */

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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