Subject: Re: [PATCH 1/1] arm64: dts: marvell: mcbin: enlarge PCI memory window

From: Thomas Petazzoni <[email-masked]>
Date: Mon, 20 May 2019 17:54:10 +0200

Hello Heinrich,

On Fri, 17 May 2019 18:11:23 +0200
Heinrich Schuchardt <[email-masked]> wrote:

> Running a graphics adapter on the MACCHIATObin fails due to an
> insufficently sized memory window.
> 
> Enlarge the memory window for the PCIe slot to 512 MiB.
> 
> With the patch I am able to use a GT710 graphics adapter with 1 GB onboard
> memory.
> 
> These are the mapped memory areas that the graphics adapter is actually
> using:
> 
> Region 0: Memory at cc000000 (32-bit, non-prefetchable) [size=16M]
> Region 1: Memory at c0000000 (64-bit, prefetchable) [size=128M]
> Region 3: Memory at c8000000 (64-bit, prefetchable) [size=32M]
> Region 5: I/O ports at 1000 [size=128]
> Expansion ROM at ca000000 [disabled] [size=512K]
> 
> Signed-off-by: Heinrich Schuchardt <[email-masked]>
> ---
>  arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
> index 329f8ceeebea..205071b45a32 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
> @@ -184,6 +184,8 @@
>  	num-lanes = <4>;
>  	num-viewport = <8>;
>  	reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
> +	ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000
> +		  0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;

While I understand the change, I find it is a bit of a "one-off"
solution, which will only work specifically for the MacchiatoBin. But
admittedly, there isn't really a good generic solution: depending on
the number of PCIe ports and what you connect to them, you will need
windows of different sizes.

On older Armada platforms, it works a bit better because we have a
single PCIe MEM aperture and a single PCIe I/O aperture, from which all
PCIe ports allocate: each PCIe interface is a child bus of an emulated
root port.

Unfortunately, on Armada 7K/8K, each PCIe interface is seen as an
independent root complex, so we have one PCIe I/O aperture and one PCIe
MEM aperture for each.

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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