From: Greg Kroah-Hartman <gregkh@linuxfoundation•org>
To: Shaokun Zhang <zhangshaokun@hisilicon•com>
Cc: "Rafael J. Wysocki" <rafael@kernel•org>,
Catalin Marinas <catalin.marinas@arm•com>,
Will Deacon <will.deacon@arm•com>,
linux-kernel@vger•kernel.org,
Jeremy Linton <jeremy.linton@arm•com>,
Sudeep Holla <sudeep.holla@arm•com>,
linux-arm-kernel@lists•infradead.org
Subject: Re: [PATCH v4 1/2] drivers: base: cacheinfo: Add variable to record max cache line size
Date: Mon, 3 Jun 2019 11:31:54 +0200 [thread overview]
Message-ID: <20190603093154.GA29175@kroah.com> (raw)
In-Reply-To: <1559009814-17004-1-git-send-email-zhangshaokun@hisilicon.com>
On Tue, May 28, 2019 at 10:16:53AM +0800, Shaokun Zhang wrote:
> Add coherency_max_size variable to record the maximum cache line size
> for different cache levels. If it is available, we will synchronize
> it as cache line size, otherwise we will use CTR_EL0.CWG reporting
> in cache_line_size() for arm64.
>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation•org>
> Cc: "Rafael J. Wysocki" <rafael@kernel•org>
> Cc: Sudeep Holla <sudeep.holla@arm•com>
> Cc: Catalin Marinas <catalin.marinas@arm•com>
> Cc: Jeremy Linton <jeremy.linton@arm•com>
> Cc: Will Deacon <will.deacon@arm•com>
> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon•com>
Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation•org>
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next prev parent reply other threads:[~2019-06-03 9:32 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-28 2:16 [PATCH v4 1/2] drivers: base: cacheinfo: Add variable to record max cache line size Shaokun Zhang
2019-05-28 2:16 ` [PATCH v4 2/2] arm64: cacheinfo: Update cache_line_size detected from DT or PPTT Shaokun Zhang
2019-06-03 9:31 ` Greg Kroah-Hartman [this message]
2019-06-04 12:45 ` [PATCH v4 1/2] drivers: base: cacheinfo: Add variable to record max cache line size Catalin Marinas
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