Subject: Re: [PATCH RFC 18/18] ARM: dts: Add minimal Raspberry Pi 4 support

From: Marc Zyngier <[email-masked]>
Date: Tue, 23 Jul 2019 19:13:26 +0100

On Wed, 17 Jul 2019 23:16:04 +0200
Stefan Wahren <[email-masked]> wrote:

> This adds minimal support for the new Raspberry Pi 4 without the
> fancy stuff like GENET, PCIe, XHCI, 40 bit DMA and V3D. The RPi 4 is available
> in 3 different variants (1, 2 and 4 GB RAM), so leave the memory size to zero
> and let the bootloader take care of it.
> 
> Other differences to the Raspberry Pi 3:
> - additional GIC 400 Interrupt controller
> - new thermal IP and HWRNG
> - additional MMC interface (emmc2)
> - additional UART, I2C, SPI and PWM interfaces
> 
> Signed-off-by: Stefan Wahren <[email-masked]>
> ---
>  arch/arm/boot/dts/Makefile            |   1 +
>  arch/arm/boot/dts/bcm2838-rpi-4-b.dts | 120 +++++++
>  arch/arm/boot/dts/bcm2838.dtsi        | 657 ++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/bcm283x.dtsi        |   2 +-
>  4 files changed, 779 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/bcm2838-rpi-4-b.dts
>  create mode 100644 arch/arm/boot/dts/bcm2838.dtsi
> 

[...]

> diff --git a/arch/arm/boot/dts/bcm2838.dtsi b/arch/arm/boot/dts/bcm2838.dtsi
> new file mode 100644
> index 0000000..e004d70
> --- /dev/null
> +++ b/arch/arm/boot/dts/bcm2838.dtsi
> @@ -0,0 +1,657 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include "bcm283x.dtsi"
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/soc/bcm2835-pm.h>
> +
> +/ {
> +	compatible = "brcm,bcm2838";
> +
> +	#address-cells = <2>;
> +	#size-cells = <1>;
> +
> +	interrupt-parent = <&gicv2>;
> +
> +	soc {
> +		ranges = <0x7e000000  0x0 0xfe000000  0x01800000>,
> +			 <0x7c000000  0x0 0xfc000000  0x02000000>,
> +			 <0x40000000  0x0 0xff800000  0x00800000>;
> +		/* Emulate a contiguous 30-bit address range for DMA */
> +		dma-ranges = <0xc0000000  0x0 0x00000000  0x3c000000>;
> +
> +		local_intc: local_intc@40000000 {
> +			compatible = "brcm,bcm2836-l1-intc";
> +			reg = <0x40000000 0x100>;
> +		};
> +
> +		gicv2: gic400@40041000 {
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			compatible = "arm,gic-400";
> +			reg =	<0x40041000 0x1000>,
> +				<0x40042000 0x2000>,
> +				<0x40044000 0x2000>,
> +				<0x40046000 0x2000>;

Missing maintenance interrupt (usually on PPI9).

> +		};

[...]

> +	arm-pmu {
> +		/*
> +		 * N.B. the A72 PMU support only exists in arch/arm64, hence
> +		 * the fallback to the A53 version.
> +		 */
> +		compatible = "arm,cortex-a72-pmu", "arm,cortex-a53-pmu";

You're thus guaranteed to count the wrong events... And you could at
least have "arm,armv8-pmuv3".

> +		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;

You're missing the interrupt-affinity property.

> +	};
> +
> +	timer {
> +		compatible = "arm,armv7-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
> +					  IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
> +					  IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
> +					  IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
> +					  IRQ_TYPE_LEVEL_LOW)>;
> +		arm,cpu-registers-not-fw-configured;

Really? :-(

> +		always-on;

I'm pretty sure that's not the case. This indicates that you can power
the CPU off, bring it back on, and yet have your timer alive and
kicking. The only case this actually exists is for VMs. I can see it
being cargo-culted from previous RPi revisions, but that doesn't make
it true.

Thanks,

	M.
-- 
Without deviation from the norm, progress is not possible.

_______________________________________________
linux-arm-kernel mailing list
[email-masked]
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel