From: Stephen Boyd <sboyd@kernel•org>
To: Andrew Jeffery <andrew@aj•id.au>, linux-clk@vger•kernel.org
Cc: linux-aspeed@lists•ozlabs.org, Andrew Jeffery <andrew@aj•id.au>,
mturquette@baylibre•com, ryanchen.aspeed@gmail•com,
linux-kernel@vger•kernel.org, Joel Stanley <joel@jms•id.au>,
linux-arm-kernel@lists•infradead.org
Subject: Re: [PATCH] clk: aspeed: Add SDIO gate
Date: Wed, 07 Aug 2019 14:15:40 -0700 [thread overview]
Message-ID: <20190807211541.5D6B0217D9@mail.kernel.org> (raw)
In-Reply-To: <20190710141009.20651-1-andrew@aj.id.au>
Quoting Andrew Jeffery (2019-07-10 07:10:09)
> From: Joel Stanley <joel@jms•id.au>
>
> The clock divisor comes with an enable bit (gate). This was not
> implemented as we didn't have access to SD hardware when writing the
> driver. Now that we can test it, add the gate as a parent to the
> divisor.
>
> There is no reason to expose the gate separately, so users will enable
> it by turning on the ASPEED_CLK_SDIO divisor.
>
> Signed-off-by: Joel Stanley <joel@jms•id.au>
> [aj: Minor style cleanup]
> Signed-off-by: Andrew Jeffery <andrew@aj•id.au>
> ---
Applied to clk-next
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prev parent reply other threads:[~2019-08-07 21:15 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-10 14:10 [PATCH] clk: aspeed: Add SDIO gate Andrew Jeffery
2019-08-07 21:15 ` Stephen Boyd [this message]
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