From: Vidya Sagar <vidyas@nvidia•com>
To: <lorenzo.pieralisi@arm•com>, <bhelgaas@google•com>,
<robh+dt@kernel•org>, <thierry.reding@gmail•com>,
<jonathanh@nvidia•com>, <andrew.murray@arm•com>
Cc: devicetree@vger•kernel.org, mmaddireddy@nvidia•com,
kthota@nvidia•com, gustavo.pimentel@synopsys•com,
vidyas@nvidia•com, linux-kernel@vger•kernel.org,
mperttunen@nvidia•com, linux-pci@vger•kernel.org,
linux-tegra@vger•kernel.org, digetx@gmail•com, kishon@ti•com,
linux-arm-kernel@lists•infradead.org, sagar.tv@gmail•com
Subject: [PATCH V4 2/6] dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries
Date: Thu, 5 Sep 2019 16:15:49 +0530 [thread overview]
Message-ID: <20190905104553.2884-3-vidyas@nvidia.com> (raw)
In-Reply-To: <20190905104553.2884-1-vidyas@nvidia.com>
Add optional bindings "vpcie3v3-supply" and "vpcie12v-supply" to describe
regulators of a PCIe slot's supplies 3.3V and 12V provided the platform
is designed to have regulator controlled slot supplies.
Signed-off-by: Vidya Sagar <vidyas@nvidia•com>
Reviewed-by: Andrew Murray <andrew.murray@arm•com>
Reviewed-by: Rob Herring <robh@kernel•org>
Acked-by: Thierry Reding <treding@nvidia•com>
---
V4:
* None
V3:
* None
V2:
* None
.../devicetree/bindings/pci/nvidia,tegra194-pcie.txt | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
index 0ac1b867ac24..b739f92da58e 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
@@ -104,6 +104,12 @@ Optional properties:
specified in microseconds
- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be
specified in microseconds
+- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot
+ if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
+ in p2972-0000 platform).
+- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot
+ if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
+ in p2972-0000 platform).
Examples:
=========
@@ -156,6 +162,8 @@ Tegra194:
0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */
vddio-pex-ctl-supply = <&vdd_1v8ao>;
+ vpcie3v3-supply = <&vdd_3v3_pcie>;
+ vpcie12v-supply = <&vdd_12v_pcie>;
phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
<&p2u_hsio_5>;
--
2.17.1
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next prev parent reply other threads:[~2019-09-05 10:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-05 10:45 [PATCH V4 0/6] PCI: tegra: Enable PCIe C5 controller of Tegra194 in p2972-0000 platform Vidya Sagar
2019-09-05 10:45 ` [PATCH V4 1/6] dt-bindings: PCI: tegra: Add sideband pins configuration entries Vidya Sagar
2019-09-05 10:45 ` Vidya Sagar [this message]
2019-09-05 10:45 ` [PATCH V4 3/6] PCI: tegra: Add support to configure sideband pins Vidya Sagar
2019-09-05 10:45 ` [PATCH V4 4/6] PCI: tegra: Add support to enable slot regulators Vidya Sagar
2019-09-05 10:45 ` [PATCH V4 5/6] arm64: tegra: Add configuration for PCIe C5 sideband signals Vidya Sagar
2019-09-05 10:45 ` [PATCH V4 6/6] arm64: tegra: Add PCIe slot supply information in p2972-0000 platform Vidya Sagar
2019-09-05 11:20 ` [PATCH V4 0/6] PCI: tegra: Enable PCIe C5 controller of Tegra194 " Lorenzo Pieralisi
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