Subject: Re: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL

From: Stephen Boyd <[email-masked]>
Date: Tue, 17 Sep 2019 22:00:40 -0700

Quoting [email-masked] (2019-09-10 23:39:20)
> From: Eugen Hristev <[email-masked]>
> 
> The PLL input range needs to be able to allow 24 Mhz crystal as input
> Update the range accordingly in plla characteristics struct
> 
> Signed-off-by: Eugen Hristev <[email-masked]>
> ---

Applied to clk-next

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