From: Catalin Marinas <catalin.marinas@arm•com>
To: Marc Zyngier <maz@kernel•org>
Cc: Mark Rutland <mark.rutland@arm•com>,
kvm@vger•kernel.org, Suzuki K Poulose <suzuki.poulose@arm•com>,
James Morse <james.morse@arm•com>,
Julien Thierry <julien.thierry.kdev@gmail•com>,
Will Deacon <will@kernel•org>,
kvmarm@lists•cs.columbia.edu,
linux-arm-kernel@lists•infradead.org
Subject: Re: [PATCH 1/5] arm64: Add ARM64_WORKAROUND_1319367 for all A57 and A72 versions
Date: Fri, 27 Sep 2019 10:03:15 +0100 [thread overview]
Message-ID: <20190927090315.GB15760@arrakis.emea.arm.com> (raw)
In-Reply-To: <20190925111941.88103-2-maz@kernel.org>
On Wed, Sep 25, 2019 at 12:19:37PM +0100, Marc Zyngier wrote:
> Rework the EL2 vector hardening that is only selected for A57 and A72
> so that the table can also be used for ARM64_WORKAROUND_1319367.
>
> Signed-off-by: Marc Zyngier <maz@kernel•org>
Acked-by: Catalin Marinas <catalin.marinas@arm•com>
--
Catalin
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next prev parent reply other threads:[~2019-09-27 9:03 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-25 11:19 [PATCH 0/5] arm64: KVM: Add workaround for errata 1319367 and 1319537 Marc Zyngier
2019-09-25 11:19 ` [PATCH 1/5] arm64: Add ARM64_WORKAROUND_1319367 for all A57 and A72 versions Marc Zyngier
2019-09-27 8:33 ` Suzuki K Poulose
2019-09-27 9:03 ` Catalin Marinas [this message]
2019-09-25 11:19 ` [PATCH 2/5] arm64: KVM: Reorder system register restoration and stage-2 activation Marc Zyngier
2019-09-25 11:19 ` [PATCH 3/5] arm64: KVM: Disable EL1 PTW when invalidating S2 TLBs Marc Zyngier
2019-10-03 11:10 ` James Morse
2019-09-25 11:19 ` [PATCH 4/5] arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context Marc Zyngier
2019-10-03 11:09 ` James Morse
2019-09-25 11:19 ` [PATCH 5/5] arm64: Enable and document ARM errata 1319367 and 1319537 Marc Zyngier
2019-09-27 9:03 ` Catalin Marinas
2019-10-03 11:11 ` James Morse
2019-10-07 9:31 ` Marc Zyngier
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