Subject: Re: [PATCH v3 4/5] clk: rockchip: add pll up and down when change pll freq

From: Stephen Boyd <[email-masked]>
Date: Thu, 03 Oct 2019 11:13:53 -0700

Quoting Elaine Zhang (2019-09-26 20:00:43)
> set pll sequence:
>         ->set pll to slow mode or other plls
>         ->set pll down
>         ->set pll params
>         ->set pll up
>         ->wait pll lock status
>         ->set pll to normal mode
> 
> To slove the system error:

solve?

> wait_pll_lock: timeout waiting for pll to lock
> pll_set_params: pll update unsucessful,
>                 trying to restore old params
> 

This commit text needs help. It looks like pseudo-code.

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