Subject: Re: [PATCH v2 04/12] arm64: docs: cpu-feature-registers: Document ID_AA64PFR1_EL1

From: Dave Martin <[email-masked]>
Date: Fri, 11 Oct 2019 15:51:49 +0100

On Fri, Oct 11, 2019 at 02:19:48PM +0100, Alex Bennée wrote:
> 
> Dave Martin <[email-masked]> writes:
> 
> > Commit d71be2b6c0e1 ("arm64: cpufeature: Detect SSBS and advertise
> > to userspace") exposes ID_AA64PFR1_EL1 to userspace, but didn't
> > update the documentation to match.
> >
> > Add it.
> >
> > Signed-off-by: Dave Martin <[email-masked]>
> >
> > ---
> >
> > Note to maintainers:
> >
> >  * This patch has been racing with various other attempts to fix
> >    the same documentation in the meantime.
> >
> >    Since this patch only fixes the documenting for pre-existing
> >    features, it can safely be dropped if appropriate.
> >
> >    The _new_ documentation relating to BTI feature reporting
> >    is in a subsequent patch, and needs to be retained.
> > ---
> >  Documentation/arm64/cpu-feature-registers.rst | 15 +++++++++++----
> >  1 file changed, 11 insertions(+), 4 deletions(-)
> >
> > diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst
> > index 2955287..b86828f 100644
> > --- a/Documentation/arm64/cpu-feature-registers.rst
> > +++ b/Documentation/arm64/cpu-feature-registers.rst
> > @@ -168,8 +168,15 @@ infrastructure:
> >       +------------------------------+---------+---------+
> >
> >
> > -  3) MIDR_EL1 - Main ID Register
> > +  3) ID_AA64PFR1_EL1 - Processor Feature Register 1
> > +     +------------------------------+---------+---------+
> > +     | Name                         |  bits   | visible |
> > +     +------------------------------+---------+---------+
> > +     | SSBS                         | [7-4]   |    y    |
> > +     +------------------------------+---------+---------+
> > +
> >
> > +  4) MIDR_EL1 - Main ID Register
> >       +------------------------------+---------+---------+
> >       | Name                         |  bits   | visible |
> >       +------------------------------+---------+---------+
> > @@ -188,7 +195,7 @@ infrastructure:
> >     as available on the CPU where it is fetched and is not a system
> >     wide safe value.
> >
> > -  4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1
> > +  5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1
> 
> If I'm not mistaken .rst has support for auto-enumeration if the #
> character is used. That might reduce the pain of re-numbering in future.

Ack, though it would be good to go one better and generate this document
from the cpufeature.c tables (or from some common source).  The numbers
are relatively easy to maintain -- remembering to update the document
at all seems the bigger maintenance headache right now.

I think this particular patch is superseded by similar fixes from other
people, just not in torvalds/master yet.

[...]

Cheers
---Dave

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