From: Xiaowei Bao <xiaowei.bao@nxp•com>
To: Zhiqiang.Hou@nxp•com, bhelgaas@google•com, robh+dt@kernel•org,
mark.rutland@arm•com, shawnguo@kernel•org, leoyang.li@nxp•com,
kishon@ti•com, lorenzo.pieralisi@arm•com, Minghuan.Lian@nxp•com,
andrew.murray@arm•com, mingkai.hu@nxp•com,
linux-pci@vger•kernel.org, linux-arm-kernel@lists•infradead.org,
devicetree@vger•kernel.org, linux-kernel@vger•kernel.org
Cc: Xiaowei Bao <xiaowei.bao@nxp•com>
Subject: [PATCH v2 2/6] dt-bindings: Add DT binding for PCIE GEN4 EP of the layerscape
Date: Tue, 15 Oct 2019 16:36:58 +0800 [thread overview]
Message-ID: <20191015083702.21792-3-xiaowei.bao@nxp.com> (raw)
In-Reply-To: <20191015083702.21792-1-xiaowei.bao@nxp.com>
Add the documentation for the Device Tree binding of the layerscape
PCIe GEN4 controller with EP mode.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp•com>
---
v2:
- remove the status entry in EP Example.
.../bindings/pci/layerscape-pcie-gen4.txt | 27 +++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
index b40fb5d..06f9309 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt
@@ -3,6 +3,8 @@ NXP Layerscape PCIe Gen4 controller
This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
the common properties defined in mobiveil-pcie.txt.
+HOST MODE
+=========
Required properties:
- compatible: should contain the platform identifier such as:
"fsl,lx2160a-pcie"
@@ -23,7 +25,20 @@ Required properties:
- msi-parent : See the generic MSI binding described in
Documentation/devicetree/bindings/interrupt-controller/msi.txt.
-Example:
+DEVICE MODE
+=========
+Required properties:
+- compatible: should contain the platform identifier such as:
+ "fsl,lx2160a-pcie-ep"
+- reg: base addresses and lengths of the PCIe controller register blocks.
+ "regs": PCIe controller registers.
+ "addr_space" EP device CPU address.
+- apio-wins: number of requested apio outbound windows.
+
+Optional Property:
+- max-functions: Maximum number of functions that can be configured (default 1).
+
+RC Example:
pcie@3400000 {
compatible = "fsl,lx2160a-pcie";
@@ -50,3 +65,13 @@ Example:
<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
};
+
+EP Example:
+
+ pcie_ep@3400000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x80 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ apio-wins = <8>;
+ };
--
2.9.5
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next prev parent reply other threads:[~2019-10-15 8:48 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-15 8:36 [PATCH v2 0/6] Add the Mobiveil EP and Layerscape Gen4 EP driver support Xiaowei Bao
2019-10-15 8:36 ` [PATCH v2 1/6] PCI: mobiveil: Add the " Xiaowei Bao
2019-10-15 8:36 ` Xiaowei Bao [this message]
2019-10-17 19:03 ` [PATCH v2 2/6] dt-bindings: Add DT binding for PCIE GEN4 EP of the layerscape Rob Herring
2019-10-18 3:54 ` Xiaowei Bao
2019-10-15 8:36 ` [PATCH v2 3/6] PCI: mobiveil: Add PCIe Gen4 EP driver for NXP Layerscape SoCs Xiaowei Bao
2019-10-15 8:37 ` [PATCH v2 4/6] PCI: mobiveil: Add workaround for unsupported request error Xiaowei Bao
2019-10-15 8:37 ` [PATCH v2 5/6] arm64: dts: lx2160a: Add PCIe EP node Xiaowei Bao
2019-10-15 8:37 ` [PATCH v2 6/6] misc: pci_endpoint_test: Add the layerscape PCIe GEN4 EP device support Xiaowei Bao
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