Subject: Re: [PATCH 2/2] iio: adc: stm32: allow to tune analog clock

From: Jonathan Cameron <[email-masked]>
Date: Sun, 3 Nov 2019 12:30:42 +0000

On Mon, 28 Oct 2019 17:11:48 +0100
Fabrice Gasnier <[email-masked]> wrote:

> Add new optional dt property to tune analog clock prescaler.
> Driver looks for optional "st,max-clk-rate-hz", then computes
> best approximation below that rate, using ADC internal prescaler.
> 
> Signed-off-by: Fabrice Gasnier <[email-masked]>
If the previous email I wrote on this got to anyone before I hit
cancel, please ignore. Had completely failed to read the code correctly.

Anyhow this seems fine to me, but given there are a lot of existing
clk related bindings I'd like to give a little longer for Rob to
have a chance to take a look at the binding.

Give me a poke if I seem to have lost this in a week or so.

Thanks,

Jonathan

> ---
>  drivers/iio/adc/stm32-adc-core.c | 16 +++++++++++++---
>  1 file changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c
> index 20c626c..6537f4f 100644
> --- a/drivers/iio/adc/stm32-adc-core.c
> +++ b/drivers/iio/adc/stm32-adc-core.c
> @@ -79,6 +79,7 @@ struct stm32_adc_priv_cfg {
>   * @domain:		irq domain reference
>   * @aclk:		clock reference for the analog circuitry
>   * @bclk:		bus clock common for all ADCs, depends on part used
> + * @max_clk_rate:	desired maximum clock rate
>   * @booster:		booster supply reference
>   * @vdd:		vdd supply reference
>   * @vdda:		vdda analog supply reference
> @@ -95,6 +96,7 @@ struct stm32_adc_priv {
>  	struct irq_domain		*domain;
>  	struct clk			*aclk;
>  	struct clk			*bclk;
> +	u32				max_clk_rate;
>  	struct regulator		*booster;
>  	struct regulator		*vdd;
>  	struct regulator		*vdda;
> @@ -141,7 +143,7 @@ static int stm32f4_adc_clk_sel(struct platform_device *pdev,
>  	}
>  
>  	for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
> -		if ((rate / stm32f4_pclk_div[i]) <= priv->cfg->max_clk_rate_hz)
> +		if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate)
>  			break;
>  	}
>  	if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
> @@ -230,7 +232,7 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
>  			if (ckmode)
>  				continue;
>  
> -			if ((rate / div) <= priv->cfg->max_clk_rate_hz)
> +			if ((rate / div) <= priv->max_clk_rate)
>  				goto out;
>  		}
>  	}
> @@ -250,7 +252,7 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
>  		if (!ckmode)
>  			continue;
>  
> -		if ((rate / div) <= priv->cfg->max_clk_rate_hz)
> +		if ((rate / div) <= priv->max_clk_rate)
>  			goto out;
>  	}
>  
> @@ -655,6 +657,7 @@ static int stm32_adc_probe(struct platform_device *pdev)
>  	struct device *dev = &pdev->dev;
>  	struct device_node *np = pdev->dev.of_node;
>  	struct resource *res;
> +	u32 max_rate;
>  	int ret;
>  
>  	if (!pdev->dev.of_node)
> @@ -731,6 +734,13 @@ static int stm32_adc_probe(struct platform_device *pdev)
>  	priv->common.vref_mv = ret / 1000;
>  	dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
>  
> +	ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz",
> +				   &max_rate);
> +	if (!ret)
> +		priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz);
> +	else
> +		priv->max_clk_rate = priv->cfg->max_clk_rate_hz;
> +
>  	ret = priv->cfg->clk_sel(pdev, priv);
>  	if (ret < 0)
>  		goto err_hw_stop;

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