Subject: Re: [PATCH v2 2/2] clk: ast2600: Add RMII RCLK gates for all four MACs

From: Stephen Boyd <[email-masked]>
Date: Fri, 08 Nov 2019 08:48:53 -0800

Quoting Andrew Jeffery (2019-10-09 19:07:25)
> RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a
> single gate for each MAC.
> 
> Signed-off-by: Andrew Jeffery <[email-masked]>
> ---

Applied to clk-next

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