Subject: Re: [PATCH v7 2/5] clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE

From: Stephen Boyd <[email-masked]>
Date: Sun, 24 Nov 2019 17:26:23 -0800

Quoting Leonard Crestez (2019-11-22 13:45:01)
> DRAM frequency switches are executed in firmware and can change the
> configuration of the DRAM PLL outside linux. Mark these CLKs with
> CLK_GET_RATE_NOCACHE so we always read back the PLL config registers and
> recalculate rates.
> 
> In current DRAM frequency tables on 8mm/8mn only the maximum frequency
> uses the PLL so it's always configured in the same way. However reading
> back the PLL configuration is the correct behavior and allows additional
> setpoints in the future.
> 
> Signed-off-by: Leonard Crestez <[email-masked]>
> Reviewed-by: Abel Vesa <[email-masked]>
> ---

Acked-by: Stephen Boyd <[email-masked]>

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