Subject: Re: [RFC PATCH 1/1] arm64: dts: added basic DTS for qmx8 congatec board

From: Oliver Graute <[email-masked]>
Date: Fri, 29 Nov 2019 08:56:49 +0100

On 28/11/19, Marc Gonzalez wrote:
> On 28/11/2019 10:55, Oliver Graute wrote:
> 
> > On 28/11/19, Marc Gonzalez wrote:
> > 
> >> On 29/10/2019 13:23, Oliver Graute wrote:
> >>
> >>> +&fec1 {
> >>> +	pinctrl-names = "default";
> >>> +	pinctrl-0 = <&pinctrl_fec1>;
> >>> +	phy-mode = "rgmii";
> >>> +	phy-handle = <&ethphy0>;
> >>> +	fsl,magic-packet;
> >>> +	fsl,rgmii_txc_dly;
> >>> +	fsl,rgmii_rxc_dly;
> >>> +	status = "okay";
> >>
> >> The two fsl,rgmii* properties do not exist in mainline.
> >> I suppose there were copied from downstream?
> > 
> > you are right, I'll remove them.
> 
> You should first check what the downstream driver does for them.
> And check if there is an equivalent action in mainline.
> These delays tend to be required for the PHY to work at all.

ok as far as I see there is currently no equilant action in mainline.
Downstream linux-imx use rgmii_txc_dly and rgmii_rxc_dly in fec_probe()
and fec_restart() for some imx8qm-fec and imx8mq-fec PHY delay quirks.
Perhaps this missing quirks are related to the random crashes in that
driver I have with imx8qm.

[  129.211959] fec 5b040000.ethernet eth0: rcv is not +last
[  129.217300] fec 5b040000.ethernet eth0: rcv is not +last
[  129.222647] fec 5b040000.ethernet eth0: rcv is not +last
[  129.227966] fec 5b040000.ethernet eth0: rcv is not +last
[  129.233282] fec 5b040000.ethernet eth0: rcv is not +last

Best regards,

Oliver

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