Subject: Re: [PATCH v2 4/7] clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs

From: Stephen Boyd <[email-masked]>
Date: Wed, 05 Feb 2020 11:33:52 -0800

Quoting Venkata Narendra Kumar Gutta (2020-01-24 14:32:24)
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 1b073b2..4258ab0 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -1367,3 +1388,172 @@ static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
>         .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
>  };
>  EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
> +
> +void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

Can we get some kernel documentation for this function?

> +                            const struct alpha_pll_config *config)
> +{
> +       if (config->l)
> +               regmap_write(regmap, PLL_L_VAL(pll), config->l);
> +
> +       regmap_write(regmap, PLL_CAL_L_VAL(pll), LUCID_PLL_CAL_VAL);
> +
> +       if (config->alpha)
> +               regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
> +
> +       if (config->config_ctl_val)
> +               regmap_write(regmap, PLL_CONFIG_CTL(pll),
> +                            config->config_ctl_val);
> +
> +       if (config->config_ctl_hi_val)
> +               regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
> +                            config->config_ctl_hi_val);
> +
> +       if (config->config_ctl_hi1_val)
> +               regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),
> +                            config->config_ctl_hi1_val);
> +
> +       if (config->user_ctl_val)
> +               regmap_write(regmap, PLL_USER_CTL(pll),
> +                            config->user_ctl_val);
> +
> +       if (config->user_ctl_hi_val)
> +               regmap_write(regmap, PLL_USER_CTL_U(pll),
> +                            config->user_ctl_hi_val);
> +
> +       if (config->user_ctl_hi1_val)
> +               regmap_write(regmap, PLL_USER_CTL_U1(pll),
> +                            config->user_ctl_hi1_val);
> +
> +       if (config->test_ctl_val)
> +               regmap_write(regmap, PLL_TEST_CTL(pll),
> +                            config->test_ctl_val);
> +
> +       if (config->test_ctl_hi_val)
> +               regmap_write(regmap, PLL_TEST_CTL_U(pll),
> +                            config->test_ctl_hi_val);
> +
> +       if (config->test_ctl_hi1_val)
> +               regmap_write(regmap, PLL_TEST_CTL_U1(pll),
> +                            config->test_ctl_hi1_val);
> +
> +       regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
> +                          PLL_UPDATE_BYPASS);
> +
> +       /* Disable PLL output */
> +       regmap_update_bits(regmap, PLL_MODE(pll),  PLL_OUTCTRL, 0);
> +
> +       /* Set operation mode to OFF */
> +       regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
> +
> +       /* PLL should be in OFF mode before continuing */
> +       wmb();

How does the write above overtake the write below? This barrier looks
wrong.

> +
> +       /* Place the PLL in STANDBY mode */
> +       regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
> +}
> +EXPORT_SYMBOL_GPL(clk_lucid_pll_configure);
> +
> +/*
> + * The Lucid PLL requires a power-on self-calibration which happens when the
> + * PLL comes out of reset. Calibrate in case it is not completed.
> + */
> +static int alpha_pll_lucid_prepare(struct clk_hw *hw)
> +{
> +       struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> +       u32 regval;
> +       int ret;
> +
> +       /* Return early if calibration is not needed. */
> +       regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &regval);
> +       if (regval & LUCID_PCAL_DONE)
> +               return 0;
> +
> +       ret = clk_trion_pll_enable(hw);
> +       if (ret)
> +               return ret;
> +
> +       clk_trion_pll_disable(hw);
> +
> +       return 0;

Can you write this like:

	/* On/off to calibrate */
	ret = clk_trion_pll_enable(hw);
	if (!ret)
		clk_trion_pll_disable(hw);

	return ret;

> +}
> +
> +static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate,
> +                                   unsigned long prate)
> +{
> +       struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> +       unsigned long rrate;
> +       u32 regval, l, alpha_width = pll_alpha_width(pll);
> +       u64 a;
> +       int ret;
> +
> +       rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
> +
> +       /*
> +        * Due to a limited number of bits for fractional rate programming, the
> +        * rounded up rate could be marginally higher than the requested rate.
> +        */
> +       if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {

Any chance this can be pushed into the alpha_pll_round_rate() API? It's
duplicated in this driver.

> +               pr_err("Call set rate on the PLL with rounded rates!\n");
> +               return -EINVAL;
> +       }
> +
> +       regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
> +       regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
> +
> +       /* Latch the PLL input */
> +       ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
> +                                PLL_UPDATE, PLL_UPDATE);
> +       if (ret)
> +               return ret;
> +
> +       /* Wait for 2 reference cycles before checking the ACK bit. */

Are reference cycles 2 * 1 / 19.2MHz?

> +       udelay(1);
> +       regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);
> +       if (!(regval & ALPHA_PLL_ACK_LATCH)) {
> +               WARN(1, "PLL latch failed. Output may be unstable!\n");

Do we need a big WARN stack for this? How about pr_warn() instead?

> +               return -EINVAL;
> +       }
> +
> +       /* Return the latch input to 0 */
> +       ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
> +                                PLL_UPDATE, 0);
> +       if (ret)
> +               return ret;
> +
> +       if (clk_hw_is_enabled(hw)) {
> +               ret = wait_for_pll_enable_lock(pll);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       /* Wait for PLL output to stabilize */
> +       udelay(100);
> +       return 0;
> +}

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