Subject: Re: [PATCH] net: ethernet: mvneta: add support for 2.5G DRSGMII mode

From: Russell King - ARM Linux admin <[email-masked]>
Date: Mon, 8 Jun 2020 17:08:01 +0100

On Mon, Jun 08, 2020 at 09:47:16AM +0200, Sascha Hauer wrote:
> The Marvell MVNETA Ethernet controller supports a 2.5 Gbps SGMII mode
> called DRSGMII.
> 
> This patch adds a corresponding phy-mode string 'drsgmii' and parses it
> from DT. The MVNETA then configures the SERDES protocol value
> accordingly.
> 
> It was successfully tested on a MV78460 connected to a FPGA.

Digging around, this is Armada XP?  Which SoCs is this mode supported?
There's no mention of DRSGMII in the A38x nor A37xx documentation which
are later than Armada XP.

What exactly is "drsgmii"?  It can't be "double-rate" SGMII because that
would give you 2Gbps max instead of the 1Gbps, but this gives 2.5Gbps,
so I'm really not sure using "drsgmii" is a good idea.  It may be what
Marvell call it, but we really need to know if there's some vendor
neutral way to refer to it.

> Signed-off-by: Sascha Hauer <[email-masked]>
> ---
>  .../devicetree/bindings/net/ethernet-controller.yaml       | 1 +
>  drivers/net/ethernet/marvell/mvneta.c                      | 7 ++++++-
>  include/linux/phy.h                                        | 3 +++
>  3 files changed, 10 insertions(+), 1 deletion(-)
> 
> This patch has already been sent 3 years ago here:
> https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email-masked]/
> Since then the driver has evolved a lot. 2.5Gbps is properly configured in the
> MAC now.

Nevertheless, adding a new interface mode needs properly documenting to
describe exactly what it is - see Documentation/networking/phy.rst, the
section "PHY interface modes".  The above point about "what is this"
illustrates why we need these documented.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTC for 0.8m (est. 1762m) line in suburbia: sync at 13.1Mbps down 424kbps up

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