Subject: Re: [RFC PATCH] pci: pci-mvebu: setup BAR0 to internal-regs

From: Thomas Petazzoni <[email-masked]>
Date: Mon, 8 Jun 2020 21:43:35 +0200

On Mon,  8 Jun 2020 17:40:25 +0300
Shmuel Hazan <[email-masked]> wrote:

> From: Shmuel H <[email-masked]>
> 
> Set the port's BAR0 address to the SOC's internal registers address. By default, this register will point to 0xd0000000, which is not correct.
> 
> Signed-off-by: Shmuel Hazan <[email-masked]>
> ---
> Sending again since I forgot to include a number of email addresses. 
> 
> Without this patch the wil6210 driver fails on interface up as follows:
> 
> # ip link set wlan0 up
> [   46.142664] wil6210 0000:01:00.0 wlan0: wil_reset: Use firmware
> <wil6210.fw> + board <wil6210.brd>
> [   48.244216] wil6210 0000:01:00.0 wlan0: wil_wait_for_fw_ready:
> Firmware not ready
> ip: SIOCSIFFLAGS: Device timeout

Do you have any idea why this particular would not work, while many
other PCIe devices do ?

> 
> With this patch, interface up succeeds:
> 
> # ip link set wlan0 up
> [   53.632667] wil6210 0000:01:00.0 wlan0: wil_reset: Use firmware
> <wil6210.fw> + board <wil6210.brd>
> [   53.666560] wil6210 0000:01:00.0 wlan0: wmi_evt_ready: FW ver.
> 5.2.0.18(SW 18); MAC 40:0e:85:c0:77:5c; 0 MID's
> [   53.676636] wil6210 0000:01:00.0 wlan0: wil_wait_for_fw_ready: FW
> ready after 20 ms. HW version 0x00000002
> [   53.686478] wil6210 0000:01:00.0 wlan0:
> wil_configure_interrupt_moderation: set ITR_TX_CNT_TRSH = 500 usec
> [   53.696191] wil6210 0000:01:00.0 wlan0:
> wil_configure_interrupt_moderation: set ITR_TX_IDL_CNT_TRSH = 13 usec
> [   53.706156] wil6210 0000:01:00.0 wlan0:
> wil_configure_interrupt_moderation: set ITR_RX_CNT_TRSH = 500 usec
> [   53.715855] wil6210 0000:01:00.0 wlan0:
> wil_configure_interrupt_moderation: set ITR_RX_IDL_CNT_TRSH = 13 usec
> [   53.725819] wil6210 0000:01:00.0 wlan0: wil_refresh_fw_capabilities:
> keep_radio_on_during_sleep (0)
> 
> Tested on Armada 38x based system.
> 
> Another related bit of information is this U-Boot commit:
> 
>   https://gitlab.denx.de/u-boot/u-boot/commit/193a1e9f196b7fb7e913a70936c8a49060a1859c
> 
> It looks like some other devices are also affected the BAR0
> initialization.
> However, by default, u-boot won't initialize any PCI bus. Which
> will cause the BAR0 register to stay on its default value. 

Perhaps you want to include more of these details in the commit log.

> diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
> index 153a64676bc9..4a00e1b81b4f 100644
> --- a/drivers/pci/controller/pci-mvebu.c
> +++ b/drivers/pci/controller/pci-mvebu.c
> @@ -203,6 +203,11 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
>  	mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
>  	mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
>  		     PCIE_BAR_CTRL_OFF(1));
> +	
> +	/* Point BAR0 to the device's internal registers (internal-regs on 
> +	 * a38x, orion and more) */
> +	mvebu_writel(port, 0xf1000000, PCIE_BAR_LO_OFF(0));

Some Armada 370/XP platforms really do use 0xd0000000 as the base
address of the internal registers. This information is available in the
DT. I think you could simply take the base address of the PCIe
controller, round down to 1 MB (which is the size of the internal
registers window) and that would give you the right address.

However, it would be good to understand this a little bit better.

Is this something you're seeing with mainline U-Boot only ? Or also
with the vendor U-Boot ? Only with this specific PCIe device ?

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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