Subject: Re: [PATCH v2 3/6] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM

From: Krzysztof Kozlowski <[email-masked]>
Date: Mon, 21 Dec 2020 14:52:32 +0100

On Mon, Dec 21, 2020 at 05:01:48PM +0530, Jagan Teki wrote:
> i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini
> from Engicam.
> 
> General features:
> - NXP i.MX8M Mini
> - Up to 2GB LDDR4
> - 8/16GB eMMC
> - Gigabit Ethernet
> - USB 2.0 Host/OTG
> - PCIe Gen2 interface
> - I2S
> - MIPI DSI to LVDS
> - rest of i.MX8M Mini features
> 
> i.Core MX8M Mini needs to mount on top of Engicam baseboards
> for creating complete platform solutions.
> 
> Add support for it.
> 
> Signed-off-by: Matteo Lisi <[email-masked]>
> Signed-off-by: Jagan Teki <[email-masked]>
> ---
> Changes for v2:
> - updated commit message
> - add cpu nodes
> - add fec1 node
> - fixed pmic tree comments
> - dropped engicam from filename since it aligned with imx6 engicam
>   dts files naming conventions.

Thanks for the changes.

> 
>  .../dts/freescale/imx8mm-icore-mx8mm.dtsi     | 232 ++++++++++++++++++
>  1 file changed, 232 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi
> new file mode 100644
> index 000000000000..e67865fd102a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-icore-mx8mm.dtsi
> @@ -0,0 +1,232 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 NXP
> + * Copyright (c) 2019 Engicam srl
> + * Copyright (c) 2020 Amarula Solutons(India)
> + */
> +
> +/ {
> +	compatible = "engicam,icore-mx8mm", "fsl,imx8mm";
> +};
> +
> +&A53_0 {
> +	cpu-supply = <&reg_buck4>;
> +};
> +
> +&A53_1 {
> +	cpu-supply = <&reg_buck4>;
> +};
> +
> +&A53_2 {
> +	cpu-supply = <&reg_buck4>;
> +};
> +
> +&A53_3 {
> +	cpu-supply = <&reg_buck4>;
> +};
> +
> +&fec1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_fec1>;
> +	phy-mode = "rgmii-id";
> +	phy-handle = <&ethphy>;
> +
> +	mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		ethphy: ethernet-phy@3 {
> +			compatible = "ethernet-phy-ieee802.3-c22";
> +			reg = <3>;
> +			reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
> +			reset-assert-us = <10000>;
> +		};
> +	};
> +};
> +
> +&i2c1 {
> +	clock-frequency = <400000>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2c1>;
> +	status = "okay";
> +
> +	pmic@8 {
> +		compatible = "nxp,pf8121a";
> +		reg = <0x08>;
> +
> +		regulators {
> +			reg_ldo1: ldo1 {
> +				regulator-max-microvolt = <5000000>;
> +				regulator-min-microvolt = <1500000>;

I mentioned previously min/max hoping it will be obvious (as most or
even all of DTS follow this convention... although not example in your
regulator) but let be more specific: first min, then max. Don't reverse
the logic. See also example in the regulator.yaml.

Best regards,
Krzysztof

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