Subject: Re: [PATCH 1/6] clk: actions: Fix UART clock dividers on Owl S500 SoC

From: Manivannan Sadhasivam <[email-masked]>
Date: Tue, 16 Mar 2021 09:20:58 +0530

On Mon, Mar 08, 2021 at 07:18:26PM +0200, Cristian Ciocaltea wrote:
> Use correct divider registers for the Actions Semi Owl S500 SoC's UART
> clocks.
> 
> Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
> Signed-off-by: Cristian Ciocaltea <[email-masked]>

Reviewed-by: Manivannan Sadhasivam <[email-masked]>

Thanks,
Mani

> ---
>  drivers/clk/actions/owl-s500.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
> index 61bb224f6330..75b7186185b0 100644
> --- a/drivers/clk/actions/owl-s500.c
> +++ b/drivers/clk/actions/owl-s500.c
> @@ -305,7 +305,7 @@ static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk",
>  static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
>  			OWL_MUX_HW(CMU_UART0CLK, 16, 1),
>  			OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
> -			OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> +			OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>  			CLK_IGNORE_UNUSED);
>  
>  static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
> @@ -317,31 +317,31 @@ static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
>  static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p,
>  			OWL_MUX_HW(CMU_UART2CLK, 16, 1),
>  			OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
> -			OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> +			OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>  			CLK_IGNORE_UNUSED);
>  
>  static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p,
>  			OWL_MUX_HW(CMU_UART3CLK, 16, 1),
>  			OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
> -			OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> +			OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>  			CLK_IGNORE_UNUSED);
>  
>  static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p,
>  			OWL_MUX_HW(CMU_UART4CLK, 16, 1),
>  			OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
> -			OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> +			OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>  			CLK_IGNORE_UNUSED);
>  
>  static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p,
>  			OWL_MUX_HW(CMU_UART5CLK, 16, 1),
>  			OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
> -			OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> +			OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>  			CLK_IGNORE_UNUSED);
>  
>  static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p,
>  			OWL_MUX_HW(CMU_UART6CLK, 16, 1),
>  			OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
> -			OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
> +			OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
>  			CLK_IGNORE_UNUSED);
>  
>  static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p,
> -- 
> 2.30.1
> 

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