Subject: Re: [RESEND PATCH net-next v4 0/3] Enable 2.5Gbps speed for stmmac

From: Vladimir Oltean <[email-masked]>
Date: Thu, 3 Jun 2021 16:28:09 +0300

Michael,

On Thu, Jun 03, 2021 at 02:08:51PM +0100, Russell King (Oracle) wrote:
> Hi,
> 
> On Thu, Jun 03, 2021 at 07:50:29PM +0800, Michael Sit Wei Hong wrote:
> > Intel mGbE supports 2.5Gbps link speed by overclocking the clock rate
> > by 2.5 times to support 2.5Gbps link speed. In this mode, the serdes/PHY
> > operates at a serial baud rate of 3.125 Gbps and the PCS data path and
> > GMII interface of the MAC operate at 312.5 MHz instead of 125 MHz.
> > This is configured in the BIOS during boot up. The kernel driver is not able
> > access to modify the clock rate for 1Gbps/2.5G mode on the fly. The way to
> > determine the current 1G/2.5G mode is by reading a dedicated adhoc
> > register through mdio bus.
> 
> How does this interact with Vladimir's "Convert xpcs to phylink_pcs_ops"
> series? Is there an inter-dependency between these, or a preferred order
> that they should be applied?
> 
> Thanks.

My preferred order would be for my series to go in first, if possible,
because I don't have hardware readily available to test, and VK already
has tested my patches a few times until they reached a stable state.

I went through your patches and I think rebasing on top of my
phylink_pcs_ops conversion should be easy.

Thanks.

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