Subject: Re: [PATCH 4/9] clk: qcom: ipq5332: Fix USB related clock defines

From: Varadarajan Narayanan <[email-masked]>
Date: Thu, 15 Jun 2023 11:32:40 +0530

On Wed, Jun 07, 2023 at 02:19:09PM +0300, Dmitry Baryshkov wrote:
> On 07/06/2023 13:56, Varadarajan Narayanan wrote:
> >Fix the USB related clock defines and add details
> >referenced by them
> >
> >Signed-off-by: Varadarajan Narayanan <[email-masked]>
> >---
> >  drivers/clk/qcom/gcc-ipq5332.c | 34 +++++++++++++++++++++++-----------
> >  1 file changed, 23 insertions(+), 11 deletions(-)
> >
> >diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
> >index a75ab88..2b58558 100644
> >--- a/drivers/clk/qcom/gcc-ipq5332.c
> >+++ b/drivers/clk/qcom/gcc-ipq5332.c
> >@@ -351,6 +351,16 @@ static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = {
> >  	{ }
> >  };
> >+static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
> >+	{ .fw_name = "usb3phy_0_cc_pipe_clk" },
> >+	{ .fw_name = "xo" },
>
> gcc-ipq5332 uses DT indices, please don't mix that with .fw_name.
>
> >+};
> >+
> >+static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
> >+	{ P_USB3PHY_0_PIPE, 0 },
> >+	{ P_XO, 2 },
> >+};
> >+
> >  static struct clk_rcg2 gcc_adss_pwm_clk_src = {
> >  	.cmd_rcgr = 0x1c004,
> >  	.mnd_width = 0,
> >@@ -1101,16 +1111,18 @@ static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {
> >  	},
> >  };
> >-static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = {
> >+static struct clk_regmap_mux usb0_pipe_clk_src = {
> >  	.reg = 0x2c074,
> >+	.shift = 8,
> >+	.width = 2,
> >+	.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
> >  	.clkr = {
> >-		.hw.init = &(struct clk_init_data) {
> >-			.name = "gcc_usb0_pipe_clk_src",
> >-			.parent_data = &(const struct clk_parent_data) {
> >-				.index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
> >-			},
> >-			.num_parents = 1,
> >-			.ops = &clk_regmap_phy_mux_ops,
> >+		.hw.init = &(const struct clk_init_data){
> >+			.name = "usb0phy_0_cc_pipe_clk_src",
> >+			.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
> >+			.num_parents = 2,
> >+			.ops = &clk_regmap_mux_closest_ops,
> >+			.flags = CLK_SET_RATE_PARENT,
> >  		},
>
> Soo... As you are reverting this. Is USB0 PIPE clock required to be parked
> to the XO? I was going to write 'before turning USB0_GDSC' off, but then I
> noticed that gcc-ipq5332 doesn't declare GDSCs. Does this platform have
> GDSCs?
>
> >  	},
> >  };
> >@@ -3041,8 +3053,8 @@ static struct clk_branch gcc_usb0_pipe_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(const struct clk_init_data) {
> >  			.name = "gcc_usb0_pipe_clk",
> >-			.parent_hws = (const struct clk_hw*[]) {
> >-				&gcc_usb0_pipe_clk_src.clkr.hw,
> >+			.parent_names = (const char *[]){
> >+				"usb0_pipe_clk_src"
>
> complete and definitive NAK. Do not use parent_names, we have just stopped
> migrating from them.

Will drop changes to this file and post a new patch.

Thanks
Varada
> >  			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >@@ -3580,7 +3592,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = {
> >  	[GCC_PCIE3X2_PIPE_CLK_SRC] = &gcc_pcie3x2_pipe_clk_src.clkr,
> >  	[GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr,
> >  	[GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr,
> >-	[GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr,
> >+	[GCC_USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
> >  };
> >  static const struct qcom_reset_map gcc_ipq5332_resets[] = {
>
> --
> With best wishes
> Dmitry
>

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