Subject: Re: [PATCH] arm64: contpte: fix set_access_flags() no-op check for SMMU/ATS faults

From: Jason Gunthorpe <[email-masked]>
Date: Tue, 3 Mar 2026 08:45:33 -0400

On Mon, Mar 02, 2026 at 11:19:46PM -0800, James Houghton wrote:

> This is similar (sort of) to a HugeTLB page fault loop I stumbled upon
> a while ago[1]. (I wonder if there have been more cases like this.)

We spent some time here looking at what the ARM spec requires, and
what kinds of HW implementations are possible..

I think the consensus is that SW must never write individual CONT PTEs
that are different from each other.

For example, a possible HW implementation could fetch a cache line of
PTEs, see the CONT bit at the VA's PTE, and then always select the
first PTE in the cache line to load the TLB.

Alternatively HW could just always load the PTE from the VA that is
faulting.

Since ARM ARM doesn't restrict this, SW must assume both possibilities
and that means it must synchronize all PTEs since it cannot predict
which PTE will be loaded by HW.

DBM will only write to a single PTE, which means HW can create
inconsistent PTEs. However if SW is fixing a fault, especially for
different walker IP (SMMU vs CPU), then it must restore the
synchronization since the PTE selection of one walker may not be
compatible with the HW update of the other.

Thus, I think any place where SW is creating inconsistent PTEs, or
leaving PTEs inconsistent after a fault is a bug.. We found a Rule
statement that seemed to require this as well.

Jason