Subject: Re: [PATCH RFC] iommu: Enable per-device SSID space for SVA

From: Jason Gunthorpe <[email-masked]>
Date: Fri, 24 Apr 2026 10:39:53 -0300

On Fri, Apr 24, 2026 at 08:53:39AM +0000, Joonwon Kang wrote:
> For SVA, the IOMMU core always allocates PASID from the global PASID
> space. The use of this global PASID space comes from the limitation of
> the ENQCMD instruction in Intel CPUs that it fetches its PASID operand
> from IA32_PASID, which is per-task.

That's right, and all the iommu drivers should have no issue with
per-device pasid or they are not following the API contract..  I
believe that has been taking care of already.

So, I don't think this is an iommu driver capability.

Instead, you have to decide if the PASID is per device or not based on
if the system will use ENQCMD or any similar instruction.  I
understand ARM has introduced a similar instruction.

So you may be better off with some kind of 'arch has enqcmd like
instruction' to control this instead of involving the iommu driver.

> - The device is not a PCIe device.
> - The device is to use SVA.
> - The supported SSID/PASID space is very small for the device; only 1 to
>   3 SSIDs are supported.

Yuk

> With this setup, when other modules have allocated all the PASIDs that
> our device is expected to use from the global PASID space via APIs like
> iommu_alloc_global_pasid() or iommu_sva_bind_device(), SVA binding to
> our device fails due to the lack of available PASIDs.

So you have multiple SVA using devices as well? Or multiple instances
of the same device?

Jason