Subject: Re: [PATCH v4 08/14] clk: sunxi-ng: a523: add system mod clocks

From: Andre Przywara <[email-masked]>
Date: Tue, 5 May 2026 18:20:17 +0200

On Tue, 5 May 2026 17:49:15 +0200
Paul Kocialkowski <[email-masked]> wrote:

Hi Paul,

> On Fri 07 Mar 25, 00:26, Andre Przywara wrote:
> > Add the clocks driving some core system related subsystems of the SoC:
> > the "CE" crypto engine, the high speed timers, the DRAM and the associated
> > MBUS clock, and the PCIe clock.
> > 
> > Signed-off-by: Andre Przywara <[email-masked]>
> > ---
> >  drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 135 +++++++++++++++++++++++++
> >  1 file changed, 135 insertions(+)
> > 
> > diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
> > index 17a4ffc0b7f52..c59f3f789d052 100644
> > --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c
> > +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c  
> 
> [...]
> 
> > +static const struct clk_parent_data hstimer_parents[] = {
> > +	{ .fw_name = "hosc" },
> > +	{ .fw_name = "iosc" },
> > +	{ .fw_name = "losc" },
> > +	{ .hw = &pll_periph0_200M_clk.hw },
> > +};
> > +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer0_clk, "hstimer0",
> > +				       hstimer_parents, 0x730,
> > +				       0, 0,	/* M */  
> 
> I was looking at the A523 ccu code and see lots of
> SUNXI_CCU_MP_DATA_WITH_MUX_GATE with no M.
> 
> Was there a particular reason for not using SUNXI_CCU_M_DATA_WITH_MUX_GATE
> instead? It would surely be less confusing.
> 
> One difference would be that the ops end up as ccu_div_ops instead of
> ccu_mp_ops. Do you need ccu_mp_ops for some reason?

Yes, please double check that (as it *is* confusing), but to me it
looks like the CCU_M_ version has just a pure divider, whereas in
CCU_MP_ the P is a *shift*, and the M a divider. Those timer clocks just
feature a shift, which I don't think we have seen before?

Cheers,
Andre