Subject: [PATCH] irqchip/mvebu: Allow EBU irqchips to be compile-tested

From: Rosen Penev <[email-masked]>
Date: Sun, 10 May 2026 12:50:47 -0700

The Marvell EBU interrupt controller Kconfig symbols are hidden and
selected only by platform code. This prevents build coverage for the
drivers on other architectures even though the code only needs OF and
MMIO support.

Add COMPILE_TEST prompts and the required dependencies for the GICP,
ICU, ODMI, PIC and SEI irqchips. While touching PIC for this coverage,
use GENMASK() and BIT() for its masks so that 32-bit platforms can
compile this safely without running into issues.

Tested: make LLVM=1 ARCH=s390 drivers/irqchip/

Assisted-by: Codex:GPT-5.5
Signed-off-by: Rosen Penev <[email-masked]>
---
 drivers/irqchip/Kconfig         | 31 ++++++++++++++++++++++++++-----
 drivers/irqchip/irq-mvebu-pic.c |  8 ++++----
 2 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index e7d559472790..cf3aea96866b 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -451,22 +451,43 @@ config MSCC_OCELOT_IRQ
 	select GENERIC_IRQ_CHIP
 
 config MVEBU_GICP
+	bool "Marvell EBU GICP interrupt controller" if COMPILE_TEST
+	depends on OF
+	depends on HAS_IOMEM
 	select IRQ_MSI_LIB
-	bool
+	help
+	  Support the Marvell EBU GICP interrupt controller.
 
 config MVEBU_ICU
-	bool
+	bool "Marvell EBU ICU interrupt controller" if COMPILE_TEST
+	depends on OF
+	depends on HAS_IOMEM
+	select GENERIC_MSI_IRQ
+	help
+	  Support the Marvell EBU ICU interrupt controller.
 
 config MVEBU_ODMI
-	bool
+	bool "Marvell EBU ODMI interrupt controller" if COMPILE_TEST
+	depends on OF
+	depends on HAS_IOMEM
 	select IRQ_MSI_LIB
 	select GENERIC_MSI_IRQ
+	help
+	  Support the Marvell EBU ODMI interrupt controller.
 
 config MVEBU_PIC
-	bool
+	bool "Marvell EBU PIC interrupt controller" if COMPILE_TEST
+	depends on OF
+	depends on HAS_IOMEM
+	help
+	  Support the Marvell EBU PIC interrupt controller.
 
 config MVEBU_SEI
-        bool
+	bool "Marvell EBU SEI interrupt controller" if COMPILE_TEST
+	depends on OF
+	depends on HAS_IOMEM
+	help
+	  Support the Marvell EBU SEI interrupt controller.
 
 config LS_EXTIRQ
 	bool "Freescale Layerscape external IRQ support" if COMPILE_TEST
diff --git a/drivers/irqchip/irq-mvebu-pic.c b/drivers/irqchip/irq-mvebu-pic.c
index 10b85128183a..95090d8efc06 100644
--- a/drivers/irqchip/irq-mvebu-pic.c
+++ b/drivers/irqchip/irq-mvebu-pic.c
@@ -24,7 +24,7 @@
 #define PIC_MASK	       0x4
 
 #define PIC_MAX_IRQS		32
-#define PIC_MAX_IRQ_MASK	((1UL << PIC_MAX_IRQS) - 1)
+#define PIC_MAX_IRQ_MASK	GENMASK(PIC_MAX_IRQS - 1, 0)
 
 struct mvebu_pic {
 	void __iomem *base;
@@ -44,7 +44,7 @@ static void mvebu_pic_eoi_irq(struct irq_data *d)
 {
 	struct mvebu_pic *pic = irq_data_get_irq_chip_data(d);
 
-	writel(1 << d->hwirq, pic->base + PIC_CAUSE);
+	writel(BIT(d->hwirq), pic->base + PIC_CAUSE);
 }
 
 static void mvebu_pic_mask_irq(struct irq_data *d)
@@ -53,7 +53,7 @@ static void mvebu_pic_mask_irq(struct irq_data *d)
 	u32 reg;
 
 	reg =  readl(pic->base + PIC_MASK);
-	reg |= (1 << d->hwirq);
+	reg |= BIT(d->hwirq);
 	writel(reg, pic->base + PIC_MASK);
 }
 
@@ -63,7 +63,7 @@ static void mvebu_pic_unmask_irq(struct irq_data *d)
 	u32 reg;
 
 	reg = readl(pic->base + PIC_MASK);
-	reg &= ~(1 << d->hwirq);
+	reg &= ~BIT(d->hwirq);
 	writel(reg, pic->base + PIC_MASK);
 }
 
-- 
2.54.0