Subject: Re: [PATCH v4 1/3] PCI: Allow ATS to be always on for CXL.cache capable devices

From: Jason Gunthorpe <[email-masked]>
Date: Wed, 20 May 2026 14:56:06 -0300

On Wed, May 20, 2026 at 12:47:58PM -0500, Bjorn Helgaas wrote:

> I don't know enough about CXL to know what's behind the ATS
> requirement.  It sounds like it's more than a simple performance
> optimization.  If you happen to know the reason, it might be worth
> a short comment about that too.

At the core of this is underlying physical interconnect protocols that
only work with translated addresses.

Ie CXL.cache only has a definition for translated physical in its
protocol spec. The use of true physical only is due to the cache
coherence shootdown protocol..

It is why I suggested 'pci_translated_required()' earlier, there are a
few more than CXl.cache why a device might need translated physical
addresses only.

ATS is the only way for a device to get those addresses, so
ats_required is fine too, but it sort of glosses over what is driving
it.

Jason