From: Ashish Mhetre <amhetre@nvidia•com>
To: <will@kernel•org>, <robin.murphy@arm•com>, <joro@8bytes•org>,
<jgg@ziepe•ca>, <nicolinc@nvidia•com>
Cc: <linux-arm-kernel@lists•infradead.org>, <iommu@lists•linux.dev>,
<linux-kernel@vger•kernel.org>, <linux-tegra@vger•kernel.org>,
Ashish Mhetre <amhetre@nvidia•com>
Subject: [PATCH v2 1/2] iommu/arm-smmu-v3: Detect Tegra264 erratum
Date: Fri, 29 May 2026 14:08:29 +0000 [thread overview]
Message-ID: <20260529140830.629738-2-amhetre@nvidia.com> (raw)
In-Reply-To: <20260529140830.629738-1-amhetre@nvidia.com>
Tegra264 SMMU is affected by erratum where a TLB entry can survive an
invalidation that races with concurrent traffic targeting the same
entry. The hardware-recommended software workaround is to issue every
CFGI/TLBI command (each followed by CMD_SYNC) twice. The second issue is
guaranteed to evict the entry. ATC_INV is not affected and must not be
doubled.
The erratum is not flagged by any SMMUv3 IDR/IIDR register, so it cannot
be detected from hardware register. Tegra264 boots from device tree only
and has no ACPI/IORT support, so detection is through device tree only.
Add the ARM_SMMU_OPT_TLBI_TWICE option and set it on instances matching
the existing "nvidia,tegra264-smmu" compatible. No callers consume the
option yet, next patch wires the workaround into the CMDQ issue paths.
Signed-off-by: Ashish Mhetre <amhetre@nvidia•com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 4 +++-
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 8 ++++++++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 9be589d14a3b..88296c0a5337 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -5229,8 +5229,10 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev,
if (of_dma_is_coherent(dev->of_node))
smmu->features |= ARM_SMMU_FEAT_COHERENCY;
- if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu"))
+ if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) {
tegra_cmdqv_dt_probe(dev->of_node, smmu);
+ smmu->options |= ARM_SMMU_OPT_TLBI_TWICE;
+ }
return ret;
}
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index 16353596e08a..08d1abaf31ae 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -928,6 +928,14 @@ struct arm_smmu_device {
#define ARM_SMMU_OPT_MSIPOLL (1 << 2)
#define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3)
#define ARM_SMMU_OPT_TEGRA241_CMDQV (1 << 4)
+/*
+ * Tegra264 erratum: a TLB entry can survive an invalidation that races
+ * with concurrent traffic targeting the same entry. The software
+ * workaround is to issue every CFGI/TLBI command twice, each followed
+ * by CMD_SYNC. The second issue is guaranteed to evict the entry.
+ * ATC_INV commands are not affected and must not be doubled.
+ */
+#define ARM_SMMU_OPT_TLBI_TWICE (1 << 5)
u32 options;
struct arm_smmu_cmdq cmdq;
--
2.50.1
next prev parent reply other threads:[~2026-05-29 14:09 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-29 14:08 [PATCH v2 0/2] iommu/arm-smmu-v3: Tegra264 invalidation workaround Ashish Mhetre
2026-05-29 14:08 ` Ashish Mhetre [this message]
2026-05-29 21:30 ` [PATCH v2 1/2] iommu/arm-smmu-v3: Detect Tegra264 erratum Nicolin Chen
2026-06-01 9:04 ` Ashish Mhetre
2026-05-29 14:08 ` [PATCH v2 2/2] iommu/arm-smmu-v3: Issue CFGI/TLBI twice on Tegra264 Ashish Mhetre
2026-05-29 21:10 ` Nicolin Chen
2026-06-01 9:20 ` Ashish Mhetre
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