Subject: [PATCH v4 0/2] perf/arm-cmn: Add workarounds for CMN-S3 on Graviton5

From: Aviv Bakal <[email-masked]>
Date: Sun, 31 May 2026 14:04:45 +0300

This series adds support for Graviton5's customised CMN-S3 which has
zeroed discovery registers.

Patch 1 is based on Robin's suggestion [1] to move the DTM index and
watchpoint bitmaps out of hw_perf_event into separate allocations,
removing the size constraint that prevented increasing CMN_MAX_DIMENSION.
Two fixes were applied on top: the kzalloc size now accounts for
sizeof(u64), and bitmap_zero() is used instead of a raw memset for
wp_idx.

Patch 2 adds the Graviton5 workarounds.

[1] https://lore.kernel.org/all/[email-masked]/

Changes since v3:
 - Replace patch 1/2 with Robin's approach: dynamically allocate
   dtm_idx and wp_idx instead of moving the struct into perf_event.h

Changes since v2:
 - Revert DTC logical ID assignment back to xp->logid (per Robin's
   review)

Aviv Bakal (2):
  perf/arm-cmn: Move DTM index data out of hw_perf_event
  perf/arm-cmn: Add workarounds for CMN-S3 on Graviton5

 drivers/perf/arm-cmn.c | 121 ++++++++++++++++++++++++++++++-----------
 1 file changed, 90 insertions(+), 31 deletions(-)

-- 
2.47.3