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From: Geetha sowjanya <gakula@marvell•com>
To: <linux-perf-users@vger•kernel.org>,
	<linux-kernel@vger•kernel.org>,
	<linux-arm-kernel@lists•infradead.org>,
	<devicetree@vger•kernel.org>
Cc: <mark.rutland@arm•com>, <will@kernel•org>, <krzk+dt@kernel•org>
Subject: [PATCH v8 3/3] perf: marvell: Cancel CN10K DDR PMU hrtimer on device remove
Date: Mon, 1 Jun 2026 13:03:18 +0530	[thread overview]
Message-ID: <20260601073318.7098-4-gakula@marvell.com> (raw)
In-Reply-To: <20260601073318.7098-1-gakula@marvell.com>

cn10k_ddr_perf_remove() did not cancel the poll hrtimer before returning.
If the device was unbound while perf events were still active the timer 
callback could run post-free.

To fix the issue by adding hrtimer_cancel() in remove().

Signed-off-by: Geetha sowjanya <gakula@marvell•com>
---

Changes in v8:
- perf: Cancel poll hrtimer in cn10k_ddr_perf_remove() to avoid use-after-free
  on device unbind (pre-existing for CN10K/Odyssey).

 drivers/perf/marvell_cn10k_ddr_pmu.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c b/drivers/perf/marvell_cn10k_ddr_pmu.c
index 6f638dfe829b..9c82bf4ee2c4 100644
--- a/drivers/perf/marvell_cn10k_ddr_pmu.c
+++ b/drivers/perf/marvell_cn10k_ddr_pmu.c
@@ -1284,6 +1284,12 @@ static void cn10k_ddr_perf_remove(struct platform_device *pdev)
 {
 	struct cn10k_ddr_pmu *ddr_pmu = platform_get_drvdata(pdev);
 
+	/*
+	 * Cancel the poll timer before further teardown so the handler
+	 * cannot run after this function returns.
+	 */
+	hrtimer_cancel(&ddr_pmu->hrtimer);
+
 	cpuhp_state_remove_instance_nocalls(
 				CPUHP_AP_PERF_ARM_MARVELL_CN10K_DDR_ONLINE,
 				&ddr_pmu->node);
-- 
2.25.1



      parent reply	other threads:[~2026-06-01  7:33 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-01  7:33 [PATCH v8 0/3] perf: marvell: Add CN20K DDR PMU support Geetha sowjanya
2026-06-01  7:33 ` [PATCH v8 1/3] dt-bindings: perf: marvell: Add CN20K DDR PMU binding Geetha sowjanya
2026-06-01  7:33 ` [PATCH v8 2/3] perf: marvell: Add CN20K DDR PMU support Geetha sowjanya
2026-06-01  7:33 ` Geetha sowjanya [this message]

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