From: Colin Huang via B4 Relay <devnull+u8813345.gmail.com@kernel•org>
To: Rob Herring <robh@kernel•org>,
Krzysztof Kozlowski <krzk+dt@kernel•org>,
Conor Dooley <conor+dt@kernel•org>,
Joel Stanley <joel@jms•id.au>,
Andrew Jeffery <andrew@codeconstruct•com.au>
Cc: devicetree@vger•kernel.org, linux-arm-kernel@lists•infradead.org,
linux-aspeed@lists•ozlabs.org, linux-kernel@vger•kernel.org,
colin.huang2@amd•com, Colin Huang <u8813345@gmail•com>
Subject: [PATCH v3 4/9] ARM: dts: aspeed: anacapa: add DVT devicetree inheriting EVT2
Date: Tue, 02 Jun 2026 21:24:59 +0800 [thread overview]
Message-ID: <20260602-anacapa-devlop-phase-devicetree-v3-4-7c93c5df8d9b@gmail.com> (raw)
In-Reply-To: <20260602-anacapa-devlop-phase-devicetree-v3-0-7c93c5df8d9b@gmail.com>
From: Colin Huang <u8813345@gmail•com>
Add a development-phase devicetree for the Facebook Anacapa BMC DVT
hardware revision and update the Anacapa wrapper DTS to reference
it.
Signed-off-by: Colin Huang <u8813345@gmail•com>
---
.../dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts | 178 +++++++++++++++++++++
.../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 2 +-
2 files changed, 179 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts
new file mode 100644
index 000000000000..0eb547ad0ec1
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dts
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
+#include "aspeed-bmc-facebook-anacapa-evt2.dts"
+
+/ {
+ model = "Facebook Anacapa BMC";
+ compatible = "facebook,anacapa-bmc-dvt", "aspeed,ast2600";
+};
+
+&sgpiom0 {
+ ngpios = <128>;
+ bus-frequency = <2000000>;
+ gpio-line-names =
+ /*in - out */
+ /* A0-A7 line 0-15 */
+ "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N",
+ "L_BNIC0_FLT", "CPU0_KBRST_N",
+ "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N",
+ "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0",
+ "L_BNIC3_FLT", "Force_I3C_SEL",
+ "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle",
+ "", "",
+ "", "",
+
+ /* B0-B7 line 16-31 */
+ "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL",
+ "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL",
+ "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL",
+ "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N",
+ "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L",
+ "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L",
+ "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330",
+ "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331",
+
+ /* C0-C7 line 32-47 */
+ "RSVD_RMC_GPIO3", "RTM_MUX_L",
+ "LEAK_DETECT_RMC_N", "RTM_MUX_R",
+ "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N",
+ "Channel6_leakage_present_CPU_DIMM", "whdt_sel",
+ "R_EAM0_NIC_CBL_PRSNT_L", "JTAG_CPLD_TRST_R_N",
+ "R_EAM1_NIC_CBL_PRSNT_L", "",
+ "L_EAM0_NIC_CBL_PRSNT_L", "",
+ "L_EAM1_NIC_CBL_PRSNT_L", "",
+
+ /* D0-D7 line 48-63 */
+ "Channel0_leakage_present_EAM3", "",
+ "Channel1_leakage_present_EAM0", "",
+ "Channel2_leakage_present_Manifold1", "",
+ "Channel4_leakage_present_Manifold2", "",
+ "AMC_BRD_PRSNT_CPLD_L", "",
+ "Channel7_leakage_present_EAM2", "",
+ "", "",
+ "", "",
+
+ /* E0-E7 line 64-79 */
+ "L_PRSNT_B_FENIC_R2_N", "",
+ "L_PRSNT_B_BENIC0_R2_N", "",
+ "L_PRSNT_B_BENIC1_R2_N", "",
+ "L_PRSNT_B_BENIC2_R2_N", "",
+ "L_PRSNT_B_BENIC3_R2_N", "",
+ "", "",
+ "", "",
+ "", "",
+
+ /* F0-F7 line 80-95 */
+ "R_PRSNT_B_FENIC_R2_N", "SGPIO_READY",
+ "R_PRSNT_B_BENIC0_R2_N", "",
+ "R_PRSNT_B_BENIC1_R2_N", "",
+ "R_PRSNT_B_BENIC2_R2_N", "",
+ "R_PRSNT_B_BENIC3_R2_N", "",
+ "", "",
+ "", "",
+ "", "",
+
+ /* G0-G7 line 96-111 */
+ "L_PRSNT_EDSFF0_N", "",
+ "L_PRSNT_EDSFF1_N", "",
+ "R_PRSNT_EDSFF2_N", "",
+ "R_PRSNT_EDSFF3_N", "",
+ "HPM_EDSFF_PG", "",
+ "", "",
+ "P12V_PWR_CABLE_PRSNT_L_R", "FM_BMC_READY_PLD",
+ "PRSNT_NFC_BOARD_R", "",
+
+ /* H0-H7 line 112-127 */
+ "R_FNIC_FLT", "",
+ "R_BNIC0_FLT", "",
+ "R_BNIC1_FLT", "",
+ "R_BNIC2_FLT", "",
+ "R_BNIC3_FLT", "",
+ "R_RTM_SW_FLT", "",
+ "RBB_Cable_Present", "",
+ "LBB_Cable_Present", "",
+
+ /* I0-I7 line 128-143 */
+ "EAM0_BRD_PRSNT_R_L", "",
+ "EAM1_BRD_PRSNT_R_L", "",
+ "EAM2_BRD_PRSNT_R_L", "",
+ "EAM3_BRD_PRSNT_R_L", "",
+ "FM_TPM_PRSNT_R_N", "",
+ "PDB_L_PRSNT_R_N", "",
+ "PRSNT_EDSFF_BOOT_N", "",
+ "PRSNT_CPU0_N", "",
+
+ /* J0-J7 line 144-159 */
+ "PRSNT_L_BRIDGE_R", "",
+ "PRSNT_R_BRIDGE_R", "",
+ "BRIDGE_L_MAIN_PG_R", "",
+ "BRIDGE_R_MAIN_PG_R", "",
+ "BRIDGE_L_STBY_PG_R", "",
+ "BRIDGE_R_STBY_PG_R", "",
+ "IRQ_NFC_BOARD_R", "",
+ "RSMRST_N", "",
+
+ /* K0-K7 line 160-175 */
+ "ADC_I2C_ALERT_N", "",
+ "TEMP_I2C_ALERT_R_L", "",
+ "CPU0_VR_SMB_ALERT_CPLD_N", "",
+ "COVER_INTRUDER_R_N", "",
+ "HANDLE_INTRUDER_CPLD_N", "",
+ "IRQ_MCIO_CPLD_WAKE_R_N", "",
+ "APML_CPU0_ALERT_R_N", "",
+ "PDB_ALERT_R_N", "",
+
+ /* L0-L7 line 176-191 */
+ "L_EDSFF0_PG", "",
+ "L_EDSFF1_PG", "",
+ "R_EDSFF2_PG", "",
+ "R_EDSFF3_PG", "",
+ "HPM_CPLD_HEART_BIT", "",
+ "RBB_CPLD_HEART_BIT", "",
+ "LBB_CPLD_HEART_BIT", "",
+ "FM_BIOS_POST_CMPLT_R_N", "",
+
+ /* M0-M7 line 192-207 */
+ "EAM0_SMERR_CPLD_R_L", "",
+ "EAM1_SMERR_CPLD_R_L", "",
+ "EAM2_SMERR_CPLD_R_L", "",
+ "EAM3_SMERR_CPLD_R_L", "",
+ "CPU0_SMERR_N_R", "",
+ "CPU0_NV_SAVE_N_R", "",
+ "PDB_PWR_LOSS_CPLD_N", "",
+ "IRQ_BMC_SMI_ACTIVE_R_N", "",
+
+ /* N0-N7 line 208-223 */
+ "AMCROT_BMC_S5_RDY_R", "",
+ "AMC_RDY_R", "",
+ "AMC_STBY_PGOOD_R", "",
+ "CPU_AMC_SLP_S5_R_L", "",
+ "AMC_CPU_EAMPG_R", "",
+ "DIMM_PMIC_PG_TIMEOUT", "",
+ "EAM_MOD_PWR_GD_TIMEOUT", "",
+ "CPLD_AMC_STBY_PWR_EN", "",
+
+ /* O0-O7 line 224-239 */
+ "HPM_PWR_FAIL", "Port80_b0",
+ "FM_DIMM_IP_FAIL", "Port80_b1",
+ "FM_DIMM_AH_FAIL", "Port80_b2",
+ "AMC_THERMTRIP_ASSERT", "Port80_b3",
+ "CPU_THERMTRIP_ASSERT", "Port80_b4",
+ "PVDDCR_SOC_P0_OCP_L", "Port80_b5",
+ "CPLD_SGPIO_RDY", "Port80_b6",
+ "FM_MAIN_PWREN_RMC_EN_ISO", "Port80_b7",
+
+ /* P0-P7 line 240-255 */
+ "CPU0_SLP_S5_N_R", "NFC_VEN",
+ "CPU0_SLP_S3_N_R", "",
+ "FM_CPU0_PWRGD", "",
+ "PWRGD_RMC", "",
+ "FM_RST_CPU0_RESET_N", "RBB_CPLD_RISCV_RST",
+ "FM_PWRGD_CPU0_PWROK", "LBB_CPLD_RISCV_RST",
+ "AMC_FAIL", "HPM_CPLD_RISCV_RST",
+ "S0_ON", "";
+
+ status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
index 1848ca347621..c74b211c42e6 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
@@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0-or-later
-#include "aspeed-bmc-facebook-anacapa-evt2.dts"
+#include "aspeed-bmc-facebook-anacapa-dvt.dts"
--
2.34.1
next prev parent reply other threads:[~2026-06-02 13:25 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-02 13:24 [PATCH v3 0/9] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang via B4 Relay
2026-06-02 13:24 ` [PATCH v3 1/9] dt-bindings: arm: aspeed: add Anacapa EVT1 EVT2 DVT board Colin Huang via B4 Relay
2026-06-02 16:20 ` Conor Dooley
2026-06-02 13:24 ` [PATCH v3 2/9] ARM: dts: aspeed: anacapa: add EVT1 devicetree and point wrapper to it Colin Huang via B4 Relay
2026-06-02 13:24 ` [PATCH v3 3/9] ARM: dts: aspeed: anacapa: add EVT2 devicetree inheriting EVT1 Colin Huang via B4 Relay
2026-06-02 13:24 ` Colin Huang via B4 Relay [this message]
2026-06-02 13:25 ` [PATCH v3 5/9] ARM: dts: aspeed: anacapa: add additional EEPROM node for SCM Colin Huang via B4 Relay
2026-06-02 13:25 ` [PATCH v3 6/9] ARM: dts: aspeed: anacapa: Add eeprom device node for NFC adaptor board Colin Huang via B4 Relay
2026-06-02 13:25 ` [PATCH v3 7/9] ARM: dts: aspeed: anacapa: Align PDB fan GPIO numbering Colin Huang via B4 Relay
2026-06-02 13:25 ` [PATCH v3 8/9] ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC Colin Huang via B4 Relay
2026-06-02 13:25 ` [PATCH v3 9/9] ARM: dts: aspeed: anacapa: evt2: add shunt resistor values for HSC monitors Colin Huang via B4 Relay
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