Subject: Re: [PATCH v7 03/13] coresight: etm4x: introduce ETM_MAX_SEQ_TRANSITIONS

From: Suzuki K Poulose <[email-masked]>
Date: Mon, 1 Jun 2026 10:53:38 +0100

On 19/05/2026 16:48, Yeoreum Yun wrote:
> According to IHI006H Embedded Trace Macrocell Architecture
> Specification [0], n could be 0-2 for TCRSEQEVR<n> when
> TCRIDR5.NUMSEQSTATE is 0b100.
> 
> Therefore, introduce ETM_MAX_SEQ_TRANSITIONS macro and apply this
> in TCRSEQEVR<n> relevant fields.
> 
> Link: https://developer.arm.com/documentation/ihi0064/latest/ [0]
> Suggestedby: Leo Yan <[email-masked]>
> Signed-off-by: Yeoreum Yun <[email-masked]>
> ---
>   drivers/hwtracing/coresight/coresight-etm4x-cfg.c | 2 +-
>   drivers/hwtracing/coresight/coresight-etm4x.h     | 5 +++--
>   2 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> index c302072b293a..e1a59b434505 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c
> @@ -76,7 +76,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata,
>   	} else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) {
>   		/* sequencer state control registers */
>   		idx = (offset & GENMASK(3, 0)) / 4;
> -		if (idx < ETM_MAX_SEQ_STATES) {
> +		if (idx < ETM_MAX_SEQ_TRANSITIONS) {
>   			reg_csdev->driver_regval = &drvcfg->seq_ctrl[idx];
>   			err = 0;
>   		}
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 89d81ce4e04e..60e08ab085c5 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -614,6 +614,7 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx)
>   #define ETM_MAX_NR_PE			8
>   #define ETMv4_MAX_CNTR			4
>   #define ETM_MAX_SEQ_STATES		4
> +#define ETM_MAX_SEQ_TRANSITIONS		(ETM_MAX_SEQ_STATES - 1)

Similar to the other comment on the patch, please don't tie this to 
SEQ_STATES. Simpl define.

#define ETM_MAX_SEQ_CTRLS		3

Suzuki

>   #define ETM_MAX_EXT_INP_SEL		4
>   #define ETM_MAX_EXT_INP			256
>   #define ETM_MAX_EXT_OUT			4
> @@ -877,7 +878,7 @@ struct etmv4_config {
>   	u32				vipcssctlr;
>   	u8				seq_idx;
>   	u8				syncfreq;
> -	u32				seq_ctrl[ETM_MAX_SEQ_STATES];
> +	u32				seq_ctrl[ETM_MAX_SEQ_TRANSITIONS];
>   	u32				seq_rst;
>   	u32				seq_state;
>   	u8				cntr_idx;
> @@ -928,7 +929,7 @@ struct etmv4_save_state {
>   	u32	trcvissctlr;
>   	u32	trcvipcssctlr;
>   
> -	u32	trcseqevr[ETM_MAX_SEQ_STATES];
> +	u32	trcseqevr[ETM_MAX_SEQ_TRANSITIONS];
>   	u32	trcseqrstevr;
>   	u32	trcseqstr;
>   	u32	trcextinselr;