Subject: Forced HW_BREAKPOINT

From: [email-masked] (Cyril Chemparathy)
Date: Wed, 01 Dec 2010 11:48:18 -0500

Hi Will,

On 12/01/2010 11:28 AM, Will Deacon wrote:
[...]
>> Yes, this CPU has a trustzone capable v6.1 debug (DIDR reads
>> 0x15121004).  The problem I am facing is that DSCR bit 15 (monitor
>> debug-mode enable bit) cannot be set, it always reads back 0x2.  As a
>> result the hw_breakpoint code spews a WARN_ON() at boot.
> 
> That's unfortunate. Is there a hardware debugger connected, or does
> the core disallow monitor debug full-stop?
> 

This was without a debugger connected.  It is possible that I have
missed some top level debug enable in the SoC (haven't traced through
the entire logic yet).

Regards
Cyril.