From: frank.rowand@am•sony.com (Frank Rowand)
To: linux-arm-kernel@lists•infradead.org
Subject: [RFC PATCH 4/6] ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUs
Date: Thu, 1 Dec 2011 11:42:32 -0800 [thread overview]
Message-ID: <4ED7D8A8.3090106@am.sony.com> (raw)
In-Reply-To: <20111201092638.GA27394@arm.com>
On 12/01/11 01:26, Catalin Marinas wrote:
> On Thu, Dec 01, 2011 at 02:57:07AM +0000, Frank Rowand wrote:
>> On 11/29/11 04:22, Catalin Marinas wrote:
>>> Since the ASIDs must be unique to an mm across all the CPUs in a system,
>>> the __new_context() function needs to broadcast a context reset event to
>>> all the CPUs during ASID allocation if a roll-over occurred. Such IPIs
>>> cannot be issued with interrupts disabled and ARM had to define
>>> __ARCH_WANT_INTERRUPTS_ON_CTXSW.
>>>
>>> This patch changes the check_context() function to
>>> check_and_switch_context() called from switch_mm(). In case of
>>> ASID-capable CPUs (ARMv6 onwards), if a new ASID is needed, it defers
>>> the __new_context() and cpu_switch_mm() calls to the post-lock switch
>>> hook where the interrupts are enabled. Setting the reserved TTBR0 was
>>> also moved to check_and_switch_context() from cpu_v7_switch_mm().
>>>
>>> Signed-off-by: Catalin Marinas <catalin.marinas@arm•com>
>>> Cc: Russell King <linux@arm•linux.org.uk>
>>> ---
>>> arch/arm/include/asm/mmu_context.h | 81 ++++++++++++++++++++++++++++--------
>>> arch/arm/include/asm/system.h | 2 +
>>> arch/arm/include/asm/thread_info.h | 1 +
>>> arch/arm/mm/context.c | 4 +-
>>> arch/arm/mm/proc-v7.S | 3 -
>>> 5 files changed, 69 insertions(+), 22 deletions(-)
>>>
>>
>> < snip >
>>
>>> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
>>> index 2faff3b..d5334d9 100644
>>> --- a/arch/arm/mm/proc-v7.S
>>> +++ b/arch/arm/mm/proc-v7.S
>>> @@ -116,9 +116,6 @@ ENTRY(cpu_v7_switch_mm)
>>> #ifdef CONFIG_ARM_ERRATA_430973
>>> mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
>>> #endif
>>> - mrc p15, 0, r2, c2, c0, 1 @ load TTB 1
>>> - mcr p15, 0, r2, c2, c0, 0 @ into TTB 0
>>> - isb
>>> #ifdef CONFIG_ARM_ERRATA_754322
>>> dsb
>>> #endif
>>
>> I do not have a tree that matches this version of cpu_v7_switch_mm().
>> Can you point me at a tree that I can see this in?
>
> That's added by the second patch in the series (and removed in a later
> patch but it is a logical change in both situations and keeps the code
> bisectable).
>
Ah, yes! Thanks.
-Frank
next prev parent reply other threads:[~2011-12-01 19:42 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-11-29 12:22 [RFC PATCH 0/6] ARM: Remove the __ARCH_WANT_INTERRUPTS_ON_CTXSW definition Catalin Marinas
2011-11-29 12:22 ` [RFC PATCH 1/6] sched: Introduce the finish_arch_post_lock_switch() scheduler hook Catalin Marinas
2011-11-29 12:22 ` [RFC PATCH 2/6] ARM: Use TTBR1 instead of reserved context ID Catalin Marinas
2011-11-29 12:22 ` [RFC PATCH 3/6] ARM: Allow ASID 0 to be allocated to tasks Catalin Marinas
2011-11-29 12:22 ` [RFC PATCH 4/6] ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUs Catalin Marinas
2011-12-01 2:57 ` Frank Rowand
2011-12-01 9:26 ` Catalin Marinas
2011-12-01 19:42 ` Frank Rowand [this message]
2011-11-29 12:22 ` [RFC PATCH 5/6] ARM: Remove current_mm per-cpu variable Catalin Marinas
2011-11-29 12:22 ` [RFC PATCH 6/6] ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on pre-ARMv6 CPUs Catalin Marinas
2011-11-29 12:48 ` [RFC PATCH 0/6] ARM: Remove the __ARCH_WANT_INTERRUPTS_ON_CTXSW definition Peter Zijlstra
2011-12-01 3:14 ` Frank Rowand
2011-12-01 9:26 ` Catalin Marinas
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