Subject: MX28 fec clock frequency

From: [email-masked] (Peter Rusko)
Date: Tue, 10 Jan 2012 14:08:31 +0100

> I'm not sure it's causing the problem you are seeing.  But from i.MX28
> spec, it seems that bit BUSY_TIME of register HW_CLKCTRL_ENET should
> be polled for new divider setting?
>

Thank you, I've added the check, but unfortunately it didn't help :(

-- 
Rusk? P?ter
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