From: aneesh@ti•com (Aneesh V)
To: linux-arm-kernel@lists•infradead.org
Subject: OMAP3 L2/outer cache enabled in kernel (after being disabled by uBoot)?
Date: Tue, 31 Jan 2012 10:51:50 +0530 [thread overview]
Message-ID: <4F277A6E.9070107@ti.com> (raw)
In-Reply-To: <20120127173029.GA3281@arm.com>
Hi Catalin,
On Friday 27 January 2012 11:00 PM, Catalin Marinas wrote:
> On Fri, Jan 20, 2012 at 08:57:11AM +0000, Joe Woodward wrote:
>>> So I re-iterate that we need to have solution to this problem.
>>
>> ... I don't want to be a pain, but it seems to me that this dicussion
>> didn't reach a full conclussion?
>
> Probably not, because it depends on many variables. See below my take on
> this.
>
>> I think it was left with the open options being:
>> 1) Leave the L2/outer cache enabled in the bootloader (not ideal and
>> may cause problems with future devices)
>
> This depends on whether the L2 is inner or outer:
>
> L2 inner - leave it enabled in the boot loader
> L2 outer - leave it disabled in the boot loader
>
>> 2) Turn the L2/outer cache on for OMAP3 later in the kernel boot when
>> the device is known
>
> Same as above:
>
> L2 inner - don't do anything, it gets used when SCTLR.M is enabled
> L2 outer - enabled at boot time via the platform code (later, after MMU
> was enabled).
>
What is the reasoning behind this recommendation? Why the distinction
between L2 being inner or outer. I don't see anything to this effect in
the Cortex-A8 TRM? In fact the only recommendation I could find(section
8.3) is asking to set L2EN to 1 before setting C bit to 1 irrespective
of inner/outer?
br,
Aneesh
next prev parent reply other threads:[~2012-01-31 5:21 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <WC20120116100344.4204CC@terrafix.co.uk>
2012-01-16 10:18 ` OMAP3 L2/outer cache enabled in kernel (after being disabled by uBoot)? Shilimkar, Santosh
2012-01-16 10:59 ` Russell King - ARM Linux
2012-01-16 12:43 ` Shilimkar, Santosh
2012-01-16 13:13 ` Russell King - ARM Linux
2012-01-16 13:22 ` Shilimkar, Santosh
2012-01-17 12:01 ` Aneesh V
[not found] ` <WC20120117085444.17057E@terrafix.co.uk>
2012-01-17 12:11 ` Catalin Marinas
2012-01-17 12:27 ` Aneesh V
2012-01-17 12:40 ` Shilimkar, Santosh
2012-01-17 13:39 ` Catalin Marinas
2012-01-17 13:58 ` Shilimkar, Santosh
2012-01-17 16:27 ` Catalin Marinas
2012-01-17 17:27 ` Shilimkar, Santosh
2012-01-17 19:39 ` Nicolas Pitre
2012-01-17 20:27 ` Shilimkar, Santosh
2012-01-17 20:45 ` Nicolas Pitre
2012-01-17 20:57 ` Nicolas Pitre
2012-01-17 20:58 ` Shilimkar, Santosh
2012-01-17 21:02 ` Nicolas Pitre
2012-01-18 8:43 ` Shilimkar, Santosh
2012-01-17 21:15 ` Russell King - ARM Linux
2012-01-17 19:47 ` Russell King - ARM Linux
2012-01-17 20:11 ` Shilimkar, Santosh
2012-01-17 20:48 ` Russell King - ARM Linux
2012-01-17 19:43 ` Russell King - ARM Linux
[not found] ` <WC20120120085711.330803@terrafix.co.uk>
2012-01-27 17:30 ` Catalin Marinas
2012-01-31 5:21 ` Aneesh V [this message]
2012-01-31 7:31 ` Catalin Marinas
2012-01-31 7:38 ` Shilimkar, Santosh
2012-01-31 8:54 ` Catalin Marinas
2012-01-31 9:05 ` Shilimkar, Santosh
2012-01-31 9:53 ` Catalin Marinas
2012-01-31 10:10 ` Russell King - ARM Linux
2012-01-31 12:10 ` Catalin Marinas
2012-01-31 18:09 ` Nicolas Pitre
2012-02-02 14:32 ` Catalin Marinas
2012-02-02 14:49 ` Russell King - ARM Linux
2012-02-02 15:10 ` Catalin Marinas
2012-01-31 9:56 ` Russell King - ARM Linux
2012-01-31 10:51 ` Shilimkar, Santosh
2012-01-31 18:27 ` Nicolas Pitre
2012-02-01 7:12 ` Shilimkar, Santosh
2012-01-17 14:18 ` Grazvydas Ignotas
2012-01-17 13:41 ` Catalin Marinas
2012-01-17 13:54 ` Aneesh V
2012-01-17 14:23 ` Måns Rullgård
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