Subject: Dove clock support

From: [email-masked] (Sebastian Hesselbarh)
Date: Tue, 19 Jun 2012 22:55:47 +0200

On 06/19/2012 10:42 PM, Simon Baatz wrote:
> Should we make this symmetric and add an enable function to gate_fn?

I also thought about that issue and I think that as long as PHY is
controlled by controller specific registers it should be handled
by the driver and not by common clock framework.

This is true for SATA and PCIe and will also remove the need for
gate_fn - as long as it doen't break other orion-based SoCs. With
ge00 on dove this is different as ge PHY is not part of the SoC
but an external chip. To turn off the external clock a clk-gate
will be required for the ge PHY bit in dove's clock control
register. This should also be a child of ge controller clock to
turn both off.

Sebastian