From: gregory.clement@free-electrons•com (Gregory CLEMENT)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl
Date: Mon, 27 Aug 2012 19:31:19 +0200 [thread overview]
Message-ID: <503BAEE7.5080401@free-electrons.com> (raw)
In-Reply-To: <5037776A.6050605@free-electrons.com>
On 08/24/2012 02:45 PM, Gregory CLEMENT wrote:
> On 08/24/2012 12:43 PM, Will Deacon wrote:> On Fri, Aug 24, 2012 at 10:09:18AM +0100, Gregory CLEMENT wrote:
>>> +static void __init aurora_broadcast_l2_commands(void)
>>> +{
>>> + __u32 u;
>>> + /* Enable Broadcasting of cache commands to L2*/
>>> + __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
>>> + u |= 0x100; /* Set the FW bit */
>>> + __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
>>> +}
>>
>> Couple of questions about this code:
>>
>> 1. Is this register r/w from non-secure?
>
> This register is banked.
>
>> 2. I'm surprised that there aren't barriers and/or maintenance operations
>> needed around this operation. It might be worth checking in the
>> documentation that you have (you probably need at least an isb()
>> following the mcr).
>
> I didn't find any mention of barriers and/or maintenance operations
> needed around this operation, but maybe I have missed something, or it
> was implicit for the people who wrote the documentation. I will ask
> confirmation that we don't need this.
I've just received confirmation that this register is r/w from non-secure.
And that it would be good practice to have an ISB after this MCR, so I
will add this for the next version coming soon.
>
>>
>> Will
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
next prev parent reply other threads:[~2012-08-27 17:31 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-24 9:09 Add support for Aurora L2 Cache Controller Gregory CLEMENT
2012-08-24 9:09 ` [PATCH 1/6] arm: cache-l2x0: make outer_cache_fns a field of l2x0_of_data Gregory CLEMENT
2012-08-24 9:09 ` [PATCH 2/6] arm: cache-l2x0: add an optional register to save/restore Gregory CLEMENT
2012-08-24 9:09 ` [PATCH 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl Gregory CLEMENT
2012-08-24 10:43 ` Will Deacon
2012-08-24 12:45 ` Gregory CLEMENT
2012-08-27 17:31 ` Gregory CLEMENT [this message]
2012-08-27 23:49 ` Will Deacon
2012-08-24 12:18 ` Sebastian Hesselbarth
2012-08-24 9:09 ` [PATCH 4/6] arm: mvebu: add L2 cache support Gregory CLEMENT
2012-08-24 9:09 ` [PATCH 5/6] arm: mvebu: add Aurora L2 Cache Controller to the DT Gregory CLEMENT
2012-08-24 14:56 ` Ian Molton
2012-08-24 15:15 ` Gregory CLEMENT
2012-08-27 9:25 ` Ian Molton
2012-08-27 17:32 ` Gregory CLEMENT
2012-08-24 9:09 ` [PATCH 6/6] arm: l2x0: add aurora related properties to OF binding Gregory CLEMENT
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