From: troy.kisky@boundarydevices•com (Troy Kisky)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 2/2] tty: serial: imx: don't reinit clock with enabled console
Date: Tue, 28 Aug 2012 11:45:24 -0700 [thread overview]
Message-ID: <503D11C4.9060508@boundarydevices.com> (raw)
In-Reply-To: <503D0D7C.2070509@boundarydevices.com>
On 8/28/2012 11:27 AM, Troy Kisky wrote:
> On 8/28/2012 3:46 AM, Dirk Behme wrote:
>> On 27.08.2012 20:20, Troy Kisky wrote:
>>> On 8/27/2012 12:36 AM, Dirk Behme wrote:
>>>> From: Xinyu Chen <xinyu.chen@freescale•com>
>>>>
>>>> Remove the imx_setup_ufcr() call on startup when CONSOLE enabled,
>>>> as this will cause clock reinit, and output garbage.
>>>>
>>>> This patch is a port from Freescale's Android kernel.
>>>>
>>>> Signed-off-by: Xinyu Chen <xinyu.chen@freescale•com>
>>>> Tested-by: Dirk Behme <dirk.behme@de•bosch.com>
>>>> CC: Shawn Guo <shawn.guo@linaro•org>
>>>> CC: Sascha Hauer <s.hauer@pengutronix•de>
>>>> ---
>>>> drivers/tty/serial/imx.c | 2 ++
>>>> 1 files changed, 2 insertions(+), 0 deletions(-)
>>>>
>>>> diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
>>>> index 908178f..31ce414 100644
>>>> --- a/drivers/tty/serial/imx.c
>>>> +++ b/drivers/tty/serial/imx.c
>>>> @@ -695,7 +695,9 @@ static int imx_startup(struct uart_port *port)
>>>> int retval;
>>>> unsigned long flags, temp;
>>>> +#ifndef CONFIG_SERIAL_CORE_CONSOLE
>>>> imx_setup_ufcr(sport, 0);
>>>> +#endif
>>>> /* disable the DREN bit (Data Ready interrupt enable) before
>>>> * requesting IRQs
>>>
>>>
>>> I'd rather do something like this
>>>
>>> static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
>>> {
>>> unsigned int val;
>>>
>>> /* set receiver / transmitter trigger level. */
>>> val = readl(sport->port.membase + UFCR) & UFCR_RFDIV;
>>
>> Shouldn't it be
>>
>> ... & (UFCR_RFDIV | UFCR_DCEDTE);
>>
>> then? My i.MX6 manual has DCEDTE as bit 6, which we don't want to
>> touch, too? We only want to touch TXTL and RXTL?
>>
>
> If you do that, you should also change imx_set_termios
> to possibly clear the bit
>
> new_ufcr = (old_ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
>
> to
>
> new_ufcr = (old_ufcr & (~(UFCR_RFDIV | UFCR_DCEDTE))) |
> UFCR_RFDIV_REG(div);
>
Sorry, I was looking at the wrong tree. Mainline does not have
sport->use_dcedte. I'm fine either way.
next prev parent reply other threads:[~2012-08-28 18:45 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-27 7:36 [PATCH 0/2] tty: serial: imx: fix lockup and garbage on SMP Dirk Behme
2012-08-27 7:36 ` [PATCH 1/2] tty: serial: imx: console write routing is unsafe " Dirk Behme
2012-08-27 22:33 ` Shawn Guo
2012-08-27 7:36 ` [PATCH 2/2] tty: serial: imx: don't reinit clock with enabled console Dirk Behme
2012-08-27 18:20 ` Troy Kisky
2012-08-28 10:46 ` Dirk Behme
2012-08-28 18:27 ` Troy Kisky
2012-08-28 18:45 ` Troy Kisky [this message]
2012-08-27 22:31 ` [PATCH 0/2] tty: serial: imx: fix lockup and garbage on SMP Shawn Guo
2012-08-27 22:51 ` Greg Kroah-Hartman
2012-08-27 23:37 ` Shawn Guo
2012-08-28 6:03 ` Dirk Behme
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