From: swarren@wwwdotorg•org (Stephen Warren)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH v2 2/2] USB: doc: Binding document for ehci-platform driver
Date: Mon, 22 Oct 2012 11:48:29 -0600 [thread overview]
Message-ID: <508586ED.1010106@wwwdotorg.org> (raw)
In-Reply-To: <Pine.LNX.4.44L0.1210221324580.1724-100000@iolanthe.rowland.org>
On 10/22/2012 11:34 AM, Alan Stern wrote:
> On Mon, 22 Oct 2012, Stephen Warren wrote:
>
>> On 10/20/2012 04:10 PM, Tony Prisk wrote:
>>> Add a binding document for ehci-platform driver.
>
>>> +Optional properties:
>>> +- caps-offset : offset to the capabilities register (default = 0)
>>> +- has-tt : controller has transaction translator(s).
>>> +- has-synopsys-hc-bug : controller has the synopsys hc bug
>>
>> That would normally be determined by the driver based on the particular
>> compatible value that is in device tree.
>
> I don't understand this comment. Isn't "has-synopsys-hc-bug" the
> compatible value in question?
"compatible value" in this context means that value of the property
named "compatible".
>>> +- big-endian : descriptors and registers are both big endian. This
>>> + is the equivalent of specifying big-endian-desc and big-endian-regs.
>>> +OR
>>> +- big-endian-desc : descriptors are in big-endian format
>>> +- big-endian-regs : mmio is in big-endian format
>>
>> Hmmm. That looks odd. Presumably if those properties aren't specified,
>> the default is little-endian? Shouldn't this be a tri-state: big,
>> little, native, with default native? I don't know what the EHCI
>> specification mandates here (and if it does mandate something, the
>> default should match the specification). Isn't this something that
>> readl/writel would take care of, or are there cases where the register
>> endianness of just this one HW block mismatches all other HW blocks?
>
> The EHCI spec assumes a PCI implementation; it doesn't consider other
> sorts. And it doesn't say anything about the endianness of multi-byte
> descriptors in memory.
OK, so does this binding default to assuming little-endian (which I
assume matches PCI), unless the big-endian properties are given? Is the
case of little-endian EHCI registers on a big-endian CPU a common enough
thing that adding a third state native-endian wouldn't be useful?
next prev parent reply other threads:[~2012-10-22 17:48 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-20 22:10 [PATCH v2 0/2] Update ehci-platform driver to support devicetree Tony Prisk
2012-10-20 22:10 ` [PATCH v2 1/2] USB: Update EHCI-platform driver to devicetree Tony Prisk
2012-10-21 2:02 ` Alan Stern
2012-10-20 22:10 ` [PATCH v2 2/2] USB: doc: Binding document for ehci-platform driver Tony Prisk
2012-10-21 17:34 ` Florian Fainelli
2012-10-22 16:07 ` Stephen Warren
2012-10-22 17:34 ` Alan Stern
2012-10-22 17:48 ` Stephen Warren [this message]
2012-10-22 19:00 ` Alan Stern
2012-10-22 22:10 ` Stephen Warren
2012-10-23 14:10 ` Alan Stern
2012-10-23 16:15 ` Stephen Warren
2012-10-23 17:59 ` Alan Stern
2012-10-23 18:47 ` Stephen Warren
2012-10-23 19:33 ` Alan Stern
2012-10-23 20:06 ` Rob Herring
2012-10-24 14:57 ` Alan Stern
2012-10-24 15:26 ` Sebastian Andrzej Siewior
2012-10-24 16:16 ` Stephen Warren
2012-10-24 16:36 ` Florian Fainelli
2012-10-24 16:38 ` Alan Stern
2012-10-24 16:44 ` Florian Fainelli
2012-10-24 18:04 ` Alan Stern
2012-10-24 18:18 ` Florian Fainelli
2012-10-24 16:45 ` Stephen Warren
2012-10-24 17:46 ` Alan Stern
2012-10-24 18:09 ` Stephen Warren
2012-10-24 18:55 ` Mitch Bradley
2012-10-24 19:30 ` Alan Stern
2012-10-25 10:23 ` Sebastian Andrzej Siewior
2012-10-25 14:36 ` Alan Stern
2012-10-26 8:02 ` Sebastian Andrzej Siewior
2012-10-26 14:54 ` Alan Stern
2012-10-25 15:53 ` Stephen Warren
2012-10-24 19:41 ` Alan Stern
2012-10-24 16:44 ` Alan Stern
2012-10-24 16:48 ` Stephen Warren
2012-10-24 17:42 ` Rob Herring
2012-10-24 17:57 ` Alan Stern
2012-10-24 16:28 ` Stephen Warren
2012-10-24 16:54 ` Alan Stern
2012-10-24 17:37 ` Florian Fainelli
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