From: santosh.shilimkar@ti•com (Santosh Shilimkar)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH V3 1/5] ARM: tegra: add pending SGI checking API
Date: Thu, 20 Dec 2012 12:46:33 +0530 [thread overview]
Message-ID: <50D2BB51.9000109@ti.com> (raw)
In-Reply-To: <CAMbhsRSDwSoHoEs93NZhDchCS28-vQCuW2p+kqfNKeqLygL2sQ@mail.gmail.com>
On Wednesday 19 December 2012 01:06 AM, Colin Cross wrote:
> On Tue, Dec 18, 2012 at 2:15 AM, Peter De Schrijver
> <pdeschrijver@nvidia•com> wrote:
>> On Tue, Dec 18, 2012 at 03:42:24AM +0100, Colin Cross wrote:
>>> On Mon, Dec 17, 2012 at 6:30 PM, Joseph Lo <josephl@nvidia•com> wrote:
>>>> The "powered-down" CPU idle mode of Tegra cut off the vdd_cpu rail, it
>>>> include the power of GIC. That caused the SGI (Software Generated
>>>> Interrupt) been lost. Because the SGI can't wake up the CPU that in
>>>> the "powered-down" CPU idle mode. We need to check if there is any
>>>> pending SGI when go into "powered-down" CPU idle mode. This is important
>>>> especially when applying the coupled cpuidle framework into "power-down"
>>>> cpuidle dirver. Because the coupled cpuidle framework may have the
>>>> chance that misses IPI_SINGLE_FUNC handling sometimes.
>>>
>>> This problem exists for any GIC-based SoC, and needs to be fixed in
>>> gic_cpu_save or gic_dist_save, whichever one loses the interrupt.
>>
>> Not necessarily. It depends on the SoC design. On Tegra20, the entire CPU
>> cluster is railgated, including the GIC. This causes a pending IPI to be lost.
>> But for example on OMAP4, only the actual CPU cores are powergated. The GIC
>> stays alive until also the core domain hits idle. By that time a potential
>> pending IPI has long woken up the target CPU again, so no additional
>> checks are needed for functional correct behavior.
>
> I'm not sure that is correct for OMAP4. C2 and C3 will put the power
> rail for the GIC in retention, and I don't think an IPI will wake it
> up. I believe the same problem also exists for Exynos5. In any case,
> checking for an IPI early during idle and aborting won't hurt those
> platforms, so I still think it should be in the GIC driver and not by
> mapping the GIC registers into a separate driver.
>
I second Colin on the GIC power states on OMAP.
Regards
Santosh
next prev parent reply other threads:[~2012-12-20 7:16 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-12-18 2:30 [PATCH V3 0/5] ARM: tegra20: cpuidle: add power-down state Joseph Lo
2012-12-18 2:30 ` [PATCH V3 1/5] ARM: tegra: add pending SGI checking API Joseph Lo
2012-12-18 2:42 ` Colin Cross
2012-12-18 2:57 ` Joseph Lo
2012-12-18 10:15 ` Peter De Schrijver
2012-12-18 19:36 ` Colin Cross
2012-12-19 1:06 ` Joseph Lo
2012-12-19 3:47 ` Joseph Lo
2012-12-20 7:16 ` Santosh Shilimkar [this message]
2012-12-20 9:34 ` Peter De Schrijver
2012-12-20 9:49 ` Santosh Shilimkar
2012-12-20 9:59 ` Peter De Schrijver
2012-12-20 10:24 ` Santosh Shilimkar
2012-12-20 11:14 ` Peter De Schrijver
2012-12-20 12:06 ` Santosh Shilimkar
2012-12-18 2:30 ` [PATCH V3 2/5] ARM: tegra20: cpuidle: add powered-down state for secondary CPU Joseph Lo
2012-12-18 2:46 ` Colin Cross
2012-12-18 3:06 ` Joseph Lo
2012-12-20 17:43 ` Stephen Warren
2012-12-21 6:36 ` Joseph Lo
2012-12-21 21:04 ` Stephen Warren
2012-12-18 2:30 ` [PATCH V3 3/5] ARM: tegra20: clocks: add CPU low-power function into tegra_cpu_car_ops Joseph Lo
2012-12-20 17:46 ` Stephen Warren
2012-12-21 5:02 ` Joseph Lo
2012-12-21 21:10 ` Stephen Warren
2012-12-18 2:31 ` [PATCH V3 4/5] ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exit Joseph Lo
2012-12-18 2:31 ` [PATCH V3 5/5] ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode Joseph Lo
2012-12-18 10:18 ` Peter De Schrijver
2012-12-20 17:54 ` Stephen Warren
2012-12-21 7:10 ` Joseph Lo
2012-12-21 21:06 ` Stephen Warren
2013-01-02 19:05 ` [PATCH V3 0/5] ARM: tegra20: cpuidle: add power-down state Stephen Warren
2013-01-03 8:39 ` Joseph Lo
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