Subject: [RFC v1] PCIe support for the Armada 370 and Armada XP SoCs

From: [email-masked] (Stephen Warren)
Date: Fri, 28 Dec 2012 16:51:24 -0700

On 12/20/2012 08:32 AM, Thierry Reding wrote:
...
> Stephen: Do you think you could dig some more, try to find out what
> the deal is with these "imprecise external aborts"? Perhaps
> something else needs to be done in order to activate the type 0
> mapping? Also, while looking through some old downstream code from
> the Vibrante area I saw a HyperTransport document mentioned that
> contains these mappings. It is referred to as the "AFI IAS"
> (section 3.2.4 is mentioned specifically). Any chance I could take
> a look at it?

I've confirmed with the HW people that on Tegra, there is no host/PCIe
bridge per se (or at least, no device that exposes PCIe
configuration-style registers, either through type 0 accesses, or a
special-case dedicated register set), and that the PCIe root ports
don't respond to type 0 configuration transactions; their PCIe config
registers must be accessed through their special-case dedicated
register set.