From: santosh.shilimkar@ti•com (Santosh Shilimkar)
To: linux-arm-kernel@lists•infradead.org
Subject: [PATCH 15/16] ARM: vexpress/dcscb: handle platform coherency exit/setup and CCI
Date: Wed, 16 Jan 2013 15:42:14 +0530 [thread overview]
Message-ID: <50F67CFE.7070109@ti.com> (raw)
In-Reply-To: <20130116100321.GA2325@e102568-lin.cambridge.arm.com>
On Wednesday 16 January 2013 03:33 PM, Lorenzo Pieralisi wrote:
> On Wed, Jan 16, 2013 at 06:33:40AM +0000, Santosh Shilimkar wrote:
>> On Tuesday 15 January 2013 11:50 PM, Dave Martin wrote:
>>> On Tue, Jan 15, 2013 at 11:53:14AM +0530, Santosh Shilimkar wrote:
>>>> On Monday 14 January 2013 05:55 PM, Lorenzo Pieralisi wrote:
>>>>> On Sat, Jan 12, 2013 at 07:21:24AM +0000, Santosh Shilimkar wrote:
>>>>>> On Saturday 12 January 2013 12:58 AM, Nicolas Pitre wrote:
>>>>>>> On Fri, 11 Jan 2013, Santosh Shilimkar wrote:
>>>>>>>
>>>>>>>> On Thursday 10 January 2013 05:50 AM, Nicolas Pitre wrote:
>>>>>>>>> From: Dave Martin <dave.martin@linaro•org>
>>>>>>>>>
>>>>>>>>> + /*
>>>>>>>>> + * Flush the local CPU cache.
>>>>>>>>> + *
>>>>>>>>> + * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
>>>>>>>>> + * a preliminary flush here for those CPUs. At least, that's
>>>>>>>>> + * the theory -- without the extra flush, Linux explodes on
>>>>>>>>> + * RTSM (maybe not needed anymore, to be investigated).
>>>>>>>>> + */
>>>>>>>> This is expected if the entire code is not in one stack frame and the
>>>>>>>> additional flush is needed to avoid possible stack corruption. This
>>>>>>>> issue has been discussed in past on the list.
>>>>>>>
>>>>>>> I missed that. Do you have a reference or pointer handy?
>>>>>>>
>>>>>>> What is strange is that this is 100% reproducible on RTSM while this
>>>>>>> apparently is not an issue on real hardware so far.
>>>>>>>
>>>>>> I tried searching archives and realized the discussion was in private
>>>>>> email thread. There are some bits and pieces on list but not all the
>>>>>> information.
>>>>>>
>>>>>> The main issue RMK pointed out is- An additional L1 flush needed
>>>>>> to avoid the effective change of view of memory when the C bit is
>>>>>> turned off, and the cache is no longer searched for local CPU accesses.
>>>>>>
>>>>>> In your case dcscb_power_down() has updated the stack which can be hit
>>>>>> in cache line and hence cache is dirty now. Then cpu_proc_fin() clears
>>>>>> the C-bit and hence for sub sequent calls the L1 cache won't be
>>>>>> searched. You then call flush_cache_all() which again updates the
>>>>>> stack but avoids searching the L1 cache. So it overwrites previous
>>>>>> saved stack frame. This seems to be an issue in your case as well.
>>>>>
>>>>> On A15/A7 even with the C bit cleared the D-cache is searched, the
>>>>> situation above cannot happen and if it does we are facing a HW/model bug.
>>>>> If this code is run on A9 then we have a problem since there, when the C bit
>>>>> is cleared D-cache is not searched (and that's why the sequence above
>>>>> should be written in assembly with no data access whatsoever), but on
>>>>> A15/A7 we do not.
>>>>>
>>>> Good point. May be model has modeled A9 and not A15 but in either
>>>> case, lets be consistent for all ARMv7 machines at least to avoid
>>>> people debugging similar issues. Many machines share code for ARMv7
>>>> processors so the best things is to stick to the sequence which works
>>>> across all ARMv7 processors.
>>>
>>> Is it sufficient to clarify the comment to indicate that the code is
>>> not directly reusable for other CPU combinations?
>>>
>> Thats not what I mean. CPU power down sequence is as per the
>> ARM specs so there shouldn't be an issue in case people
>> find it useful for other purposes. Thats other topc though.
>
> If they run it on an A9 there is an issue and as hotplug code for
> vexpress proved, copy'n'paste is a real danger.
>
>>
>>> DCSCB is incredibly platform-specific, and we would not expect to
>>> see it in other platforms.
>
> Agreed, but it is also the first example of power API implementation.
> Stubbing out this code in an assembly file valid for all v7 implementations
> is simple, provided we consider that worthwhile. I do. Or at least I can
> write the sequence up in /Documentation, how it should be done to be generic
> and describe the pitfalls.
>
>>>
>>> Or do we consider the risk of people copying this code verbatim
>>> (including the "do not copy this code" comment) too high?
>>>
>> I am not sure what exactly you mean. We are discussing the sequence
>> here on the basis of additional L1 cache flush. As mentioned
>> clearly the documentation is the ARM ARM(which is generic for
>> all ARMv7) missing to capture the need of the power
>> down code and stack usage which at least creates an issue on
>> A9. Documenting that in code and mainly in ARM specs would avoid
>> any further confusions.
>
> Power down sequence is defined explicitly in A15 and A7 TRMs. I do not
> think they should write "do not use the stack or cacheable memory that
> can result in dirty lines" in betweeen the power down steps. Once you
> know the C bit behaviour coding follows. True, they might add this for
> A9, and I asked that, to no avail, for internal reasons.
>
Fair enough.
> Documenting it in the kernel won't hurt either. And to answer Dave, I
> think that copy'n'paste verbatim is a risk we should not run, unless we
> are willing to be on the lookout for bugs. I can write up some documentation
> that we can merge along with the power API.
>
+1
Regards,
Santosh
next prev parent reply other threads:[~2013-01-16 10:12 UTC|newest]
Thread overview: 132+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-10 0:20 [PATCH 00/16] big.LITTLE low-level CPU and cluster power management Nicolas Pitre
2013-01-10 0:20 ` [PATCH 01/16] ARM: b.L: secondary kernel entry code Nicolas Pitre
2013-01-10 7:12 ` Stephen Boyd
2013-01-10 15:30 ` Nicolas Pitre
2013-01-10 15:34 ` Catalin Marinas
2013-01-10 16:47 ` Nicolas Pitre
2013-01-11 11:45 ` Catalin Marinas
2013-01-11 12:05 ` Lorenzo Pieralisi
2013-01-11 12:19 ` Dave Martin
2013-01-10 23:05 ` Will Deacon
2013-01-11 1:26 ` Nicolas Pitre
2013-01-11 10:55 ` Will Deacon
2013-01-11 11:35 ` Dave Martin
2013-01-11 17:16 ` Santosh Shilimkar
2013-01-11 18:10 ` Nicolas Pitre
2013-01-11 18:30 ` Santosh Shilimkar
2013-03-07 7:37 ` Pavel Machek
2013-03-07 8:57 ` Nicolas Pitre
2013-01-10 0:20 ` [PATCH 02/16] ARM: b.L: introduce the CPU/cluster power API Nicolas Pitre
2013-01-10 23:08 ` Will Deacon
2013-01-11 2:30 ` Nicolas Pitre
2013-01-11 10:58 ` Will Deacon
2013-01-11 11:29 ` Dave Martin
2013-01-11 17:26 ` Santosh Shilimkar
2013-01-11 18:33 ` Nicolas Pitre
2013-01-11 18:41 ` Santosh Shilimkar
2013-01-11 19:54 ` Nicolas Pitre
2013-01-10 0:20 ` [PATCH 03/16] ARM: b.L: introduce helpers for platform coherency exit/setup Nicolas Pitre
2013-01-10 12:01 ` Dave Martin
2013-01-10 19:04 ` Nicolas Pitre
2013-01-11 11:30 ` Dave Martin
2013-01-10 16:53 ` Catalin Marinas
2013-01-10 17:59 ` Nicolas Pitre
2013-01-10 21:50 ` Catalin Marinas
2013-01-10 22:31 ` Nicolas Pitre
2013-01-11 10:36 ` Dave Martin
2013-01-10 22:32 ` Nicolas Pitre
2013-01-10 23:13 ` Will Deacon
2013-01-11 1:50 ` Nicolas Pitre
2013-01-11 11:09 ` Dave Martin
2013-01-11 17:46 ` Santosh Shilimkar
2013-01-11 18:07 ` Dave Martin
2013-01-11 18:34 ` Santosh Shilimkar
2013-01-14 17:08 ` Dave Martin
2013-01-14 17:15 ` Catalin Marinas
2013-01-14 18:10 ` Dave Martin
2013-01-14 21:34 ` Catalin Marinas
2013-01-10 0:20 ` [PATCH 04/16] ARM: b.L: Add baremetal voting mutexes Nicolas Pitre
2013-01-10 23:18 ` Will Deacon
2013-01-11 3:15 ` Nicolas Pitre
2013-01-11 11:03 ` Will Deacon
2013-01-11 16:57 ` Dave Martin
2013-01-10 0:20 ` [PATCH 05/16] ARM: bL_head: vlock-based first man election Nicolas Pitre
2013-01-10 0:20 ` [PATCH 06/16] ARM: b.L: generic SMP secondary bringup and hotplug support Nicolas Pitre
2013-01-11 18:02 ` Santosh Shilimkar
2013-01-14 18:05 ` Achin Gupta
2013-01-15 6:32 ` Santosh Shilimkar
2013-01-15 11:18 ` Achin Gupta
2013-01-15 11:26 ` Santosh Shilimkar
2013-01-15 18:53 ` Dave Martin
2013-01-14 16:35 ` Will Deacon
2013-01-14 16:51 ` Nicolas Pitre
2013-01-15 19:09 ` Dave Martin
2013-01-10 0:20 ` [PATCH 07/16] ARM: bL_platsmp.c: close the kernel entry gate before hot-unplugging a CPU Nicolas Pitre
2013-01-14 16:37 ` Will Deacon
2013-01-14 16:53 ` Nicolas Pitre
2013-01-14 17:00 ` Will Deacon
2013-01-14 17:11 ` Catalin Marinas
2013-01-14 17:15 ` Nicolas Pitre
2013-01-14 17:23 ` Will Deacon
2013-01-14 18:26 ` Russell King - ARM Linux
2013-01-14 18:49 ` Nicolas Pitre
2013-01-15 18:40 ` Dave Martin
2013-01-16 16:06 ` Catalin Marinas
2013-01-10 0:20 ` [PATCH 08/16] ARM: bL_platsmp.c: make sure the GIC interface of a dying CPU is disabled Nicolas Pitre
2013-01-11 18:07 ` Santosh Shilimkar
2013-01-11 19:07 ` Nicolas Pitre
2013-01-12 6:50 ` Santosh Shilimkar
2013-01-12 16:47 ` Nicolas Pitre
2013-01-13 4:37 ` Santosh Shilimkar
2013-01-14 17:53 ` Lorenzo Pieralisi
2013-01-14 16:39 ` Will Deacon
2013-01-14 16:54 ` Nicolas Pitre
2013-01-14 17:02 ` Will Deacon
2013-01-14 17:18 ` Nicolas Pitre
2013-01-14 17:24 ` Will Deacon
2013-01-14 17:56 ` Lorenzo Pieralisi
2013-01-10 0:20 ` [PATCH 09/16] ARM: vexpress: Select the correct SMP operations at run-time Nicolas Pitre
2013-01-10 0:20 ` [PATCH 10/16] ARM: vexpress: introduce DCSCB support Nicolas Pitre
2013-01-11 18:12 ` Santosh Shilimkar
2013-01-11 19:13 ` Nicolas Pitre
2013-01-12 6:52 ` Santosh Shilimkar
2013-01-10 0:20 ` [PATCH 11/16] ARM: vexpress/dcscb: add CPU use counts to the power up/down API implementation Nicolas Pitre
2013-01-10 0:20 ` [PATCH 12/16] ARM: vexpress/dcscb: do not hardcode number of CPUs per cluster Nicolas Pitre
2013-01-10 0:20 ` [PATCH 13/16] drivers: misc: add ARM CCI support Nicolas Pitre
2013-01-11 18:20 ` Santosh Shilimkar
2013-01-11 19:22 ` Nicolas Pitre
2013-01-12 6:53 ` Santosh Shilimkar
2013-01-15 18:34 ` Dave Martin
2013-01-10 0:20 ` [PATCH 14/16] ARM: TC2: ensure powerdown-time data is flushed from cache Nicolas Pitre
2013-01-10 18:50 ` Dave Martin
2013-01-10 19:13 ` Nicolas Pitre
2013-01-11 11:38 ` Dave Martin
2013-01-10 0:20 ` [PATCH 15/16] ARM: vexpress/dcscb: handle platform coherency exit/setup and CCI Nicolas Pitre
2013-01-10 12:05 ` Dave Martin
2013-01-11 18:27 ` Santosh Shilimkar
2013-01-11 19:28 ` Nicolas Pitre
2013-01-12 7:21 ` Santosh Shilimkar
2013-01-14 12:25 ` Lorenzo Pieralisi
2013-01-15 6:23 ` Santosh Shilimkar
2013-01-15 18:20 ` Dave Martin
2013-01-16 6:33 ` Santosh Shilimkar
2013-01-16 10:03 ` Lorenzo Pieralisi
2013-01-16 10:12 ` Santosh Shilimkar [this message]
2013-01-10 0:20 ` [PATCH 16/16] ARM: vexpress/dcscb: probe via device tree Nicolas Pitre
2013-01-10 0:46 ` [PATCH 00/16] big.LITTLE low-level CPU and cluster power management Rob Herring
2013-01-10 5:04 ` Nicolas Pitre
2013-01-10 23:01 ` Will Deacon
2013-01-14 9:56 ` Joseph Lo
2013-01-14 14:05 ` Nicolas Pitre
2013-01-15 2:44 ` Joseph Lo
2013-01-15 16:44 ` Nicolas Pitre
2013-01-16 16:02 ` Catalin Marinas
2013-01-16 21:18 ` Nicolas Pitre
2013-01-17 17:55 ` Catalin Marinas
2013-01-15 18:31 ` Dave Martin
2013-03-07 8:27 ` Pavel Machek
2013-03-07 9:12 ` Nicolas Pitre
2013-03-07 9:40 ` Pavel Machek
2013-03-07 9:56 ` Nicolas Pitre
2013-03-07 14:51 ` Pavel Machek
2013-03-07 15:42 ` Nicolas Pitre
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