Subject: [PATCH 05/17] ARM: fixup_pv_table bug when CPU_ENDIAN_BE8

From: [email-masked] (Ben Dooks)
Date: Mon, 11 Feb 2013 19:11:58 +0000

On 09/02/13 03:40, Nicolas Pitre wrote:
> On Fri, 8 Feb 2013, Ben Dooks wrote:
>
>> The fixup_pv_table assumes that the instructions are in the same
>> endian configuration as the data, but when the CPU is running in
>> BE8 the instructions stay in little-endian format.
>>
>> Make sure if CONFIG_CPU_ENDIAN_BE8 is set that we do all the
>> alterations to the instructions taking in to account the LDR/STR
>> will be swapping the data endian-ness.
>>
>> Since the code is only modifying a byte, we avoid dual-swapping
>> the data, and just change the bits we clear and ORR in.
>>
>> Note, not tested against an actual bug, it looked wrong.
>
> You are missing the CONFIG_THUMB2_KERNEL counterpart.

Sorry, I will have a look into that, although I may need
some help on that as I don't have any experience with
CONFIG_THUMB2_KERNEL or a userland to test with.

>> Signed-off-by: Ben Dooks<[email-masked]>
>> ---
>>   arch/arm/kernel/head.S |    6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
>> index f1ab279..aafb151 100644
>> --- a/arch/arm/kernel/head.S
>> +++ b/arch/arm/kernel/head.S
>> @@ -579,8 +579,14 @@ __fixup_a_pv_table:
>>   #else
>>   	b	2f
>>   1:	ldr	ip, [r7, r3]
>> +#ifdef CONFIG_CPU_ENDIAN_BE8
>> +	@ in BE8, we load data in BE, but instructions still in LE
>> +	bic	ip, ip, #0xff000000
>> +	orr	ip, ip, r6, lsl#24
>> +#else
>>   	bic	ip, ip, #0x000000ff
>>   	orr	ip, ip, r6	@ mask in offset bits 31-24
>> +#endif
>>   	str	ip, [r7, r3]
>>   2:	cmp	r4, r5
>>   	ldrcc	r7, [r4], #4	@ use branch for delay slot
>> --
>> 1.7.10.4
>>
>>
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>>
>
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-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius