Subject: [PATCH] ARM: vfp: fix fpsid register subarchitecture field mask width

From: [email-masked] (Stephen Boyd)
Date: Tue, 26 Feb 2013 17:37:17 -0800

On 02/25/13 12:02, Russell King - ARM Linux wrote:
>
> This can of worms is getting bigger.  We have more problems with our
> handling of the different VFP versions, specifically the handling of
> the EX=0 DEX=0 case.
>
> VFP common subarch 3 defines the EX=0, DEX=0 encoding to mean one of
> the following conditions have been met:
>
> 1. an unallocated VFP instruction was encountered.
>
>    In other words, the VFP was the target of the co-processor instruction,
>    but the instruction is not a known VFP instruction encoding.  This
>    should raise an undefined instruction exception.
>
> 2. an allocated VFP instruction was encountered, but not handled in
>    hardware.
>
>    In other words, the instruction is a valid VFP instruction, but the
>    hardware has opted not to implement this instruction and wants
>    software to emulate it instead.
>
>    (Note: this can also be raised as EX=0, DEX=1 - implementation
>     defined!)
>
[snip]
>
> So, if EX or DEX is set, _or_ IXE is set, we pass control to VFP_bounce.
> This is problematical.
>
> (a) condition (2) above isn't correctly handled for common subarch v3 - it
>     is always treated as an undefined instruction, and will result in a
>     SIGILL being delivered.
>
[snip]
>
> Now, (a) is just bad behaviour - as we haven't had any reports of this
> yet, I suspect that no one has implemented VFP hardware with this
> behaviour yet.

I believe we ran into this a while ago and fixed it for our chips. We
never sent the patch upstream. Sorry.

https://www.codeaurora.org/gitweb/quic/la/?p=kernel/msm.git;a=commitdiff;h=00a13be874f230159a6b7f8cc9d0ff23bc1b7d05

I'm looking into what our bits correspond to. Hopefully get back to you
in 20 something hours.

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